This study delves into the impact of interconnects on Ferroelectric Field-Effect Transistor (FeFET) devices, employing ferroelectric materials in the gate stack for non-volatile memory at the 3nm technology node. Specifically, the study investigates the impact of interconnect on Logic-in-Memory (LiM) circuits. As the impact of interconnect become more pronounced at sub-nanometer scales, they are known to have a significant influence on circuit characteristics beyond the intrinsic properties of the components. Leveraging a newly developed path-finding process-design-kit (PDK), encompassing FeFET characteristics and interconnect properties, we explored various circuit configurations such as full-adder (FA) and ternary content-addressable memory (TCAM). Our investigation revealed that FeFET-based LiM circuits offer advantages in area, propagation delay, and power consumption compared to traditional CMOS-based circuits. While interconnects still influence FeFET-based circuit characteristics, their impact is somewhat tempered in comparison. We meticulously quantified these impacts. The simulation of how the next generation of advanced interconnect processes can further enhance FeFET-based LiM circuit performance was conducted using the PDK. Through this analysis, we proposed guidelines for the layout design of future FeFET-based LiM circuits.

Computing-in-memory (CIM) may offer a power-efficient solution to the acceleration of major workloads for memory-bound deep neural networks given memory and processing units on the same die, particularly, when incorporating the processing units into the memory domains. Further, CIM macros utilizing nonvolatile memory with multibit data significantly boost their data density and realize zero standby power by gating power when idle. Ferroelectric Field-Effect-Transistor (FeFET) is a leading contender for this type of CIM. In this work, we designed mixed signal CIM macros based on FeFETs and identified their optimal performance with the size of a sub-array (nM× nw) addressed at one cycle, where nwis the number of FeFETs representing a single w-bit weight. The simulations performed identified the optimal sub-array $n_M^{\ast} \times w/2$ for w-bit weights with different $n_M^{\ast}$ (i.e., parallelism) for different weight resolution w, which highlights a ∼29× improvement in figure of merit for 8-bit weights compared with the case of no weight-splitting (nw= 1).