Deep neural network (DNN) accelerators integrated with RISC-V Instruction Set Architecture (ISA) extensions have enabled efficient computing on resource-constrained platforms. However, their specialization in regular compute patterns limits effectiveness on irregular workloads, making it challenging to achieve high throughput and energy efficiency. To tackle these challenges, we present ReNN-RV, which integrates a computation-aware RISC-V ISA extension with an instructiondriven processing pipeline to efficiently accelerate run-time reconfigurable processing elements (RePEs). The computation-aware ISA employs configurable opcodes and custom encodings to support fine-grained task scheduling, while an instructiondriven pipeline implements it with minimal control complexity. Moreover, theRePEaccelerator provides seamless switching between multiply-accumulate (MAC) and non-MAC operations by configuring a path multiplexer to realize multiple operators at run time. Experimental results demonstrate that ReNN-RV achieves average reductions of 14.6× in cycle count and 15.3× in execution time across representative DNN workloads compared with the baseline RISC-V design. On average, ReNN-RV outperforms state-of-the-art designs by 10.1× for energy efficiency and 10.3× for computational throughput.

This paper describes a fully synthesizable digital-to-analog converter (DAC). It is important to develop an automated netlist generation and synthesizable design methodology for mixed-signal circuits. To fill in the scarcity of synthesizable DACs, we propose a multi-bit full-synthesizable current DAC using shifting current mirror architecture with a multi-segmented data weighted averaging (MSeDWA) mismatch correction algorithm. It provides robustness against process, voltage, and temperature (PVT) variations by means of a programmable bias generator, which suppresses the circuit variations by >2.7 ×. The use of power-gating standard cells provides a flexible selection of current mirror types, thus achieving a widening of the voltage operation range. Moreover, stage separation and appropriate gain configuration ensure high linearity.With the MSeDWA technique, the total harmonic distortion (THD) is further improved by 7.7 dB. Operating between 14 MHz to 56 MHz, the analog and digital circuits consume 8.64-56.64 μW and 217-629 μW, respectively. The proposed circuit has demonstrated an excellent energy efficiency of 0.03 μW/kHz while maintaining a maximum THD of 39.9 dB (1.01%).

The lithography process inherently introduces device-to-device variation in the fabrication of resistive random-access memory (RRAM) array, introducing electrical mismatch and limiting the practical applications of RRAM-based analog computing circuits. In this work, we propose a lithography model-aware layout synthesis framework to minimize the proximity effect in the lithography process, thus reducing the electrical mismatch amongst these devices for analog computing applications. A dummy RRAM cell insertion technique is proposed to reduce the geometrical mismatch among RRAM cells, and a bi-objective alternate optimization method is proposed to efficiently optimize the geometric parameters and the structure of RRAM layouts. In addition, an approximation method for evaluating the quality of the RRAM array layout is proposed to reduce the runtime of synthesis. The experimental results show that our proposed framework significantly reduces the deviation between printed and expected patterns.

True Random Number Generators (TRNGs) are essential components of modern cryptographic and security systems, where the unpredictability and statistical quality of generated randomness directly determine the resilience of the system against attacks. This paper presents the TeLo-ROPN (Tent and Logistic–Ring Oscillator Parallel Network) TRNG system, a chaotic-map-enhanced TRNG for FPGA-based cryptographic applications. The proposed architecture integrates two discretized chaotic maps, Tent and Logistic, dynamically coupled through delayed feedback, with a ROPN module serving as the primary entropy source. The proposed TeLo-ROPN TRNG design was implemented on an Intel Cyclone V GT FPGA (5CGXFC9D6F27C7) and achieved near-ideal entropy, measuring 7.9991078 bits/byte in the AIS-31 T8 test and 7.963200bits/byte in the NIST SP 800-90B test. It successfully passed all NIST SP 800-22 statistical tests and demonstrated an energy efficiency of 16.97 pJ/bit at 300 MHz. The delayed chaotic interaction enhances resilience against modeling attacks, while the modular structure minimizes hardware overhead. These results demonstrate that TeLo-ROPN TRNG provides a high-throughput and energy-efficient solution for secure embedded and cryptographic systems.

Compact models of transistors are essential for simulating and optimizing circuits with the use of SPICE simulation tool. Parameter extraction, which is calibrating these models, is essential to ensure their alignment with measured or simulated data. However, conventional parameter extraction methods are generally iterative and experience-dependent, requiring significant time and effort from modeling engineers. Moreover, as semiconductor devices and compact models become increasingly advanced, the need for a tailored extraction process for each model has become increasingly inefficient. To address the above challenges, this work proposes an agile transistor compact modeling framework, ATMAD. The proposed framework takes a compact model file and a set of electrical characteristic data as inputs, producing a calibrated model with minimal human intervention. ATMAD automatically retrieves the equations in the compact model and converts them into computational flow graphs, thus supporting different compact models with a generalized process. A graph unlooping technique is proposed to support automatic differentiation for compact models with implicit functions (e.g., series resistance and surface potential solving). Based on the computational flow graph, ATMAD adopts automatic differentiation technique to achieve automatic and parallel optimization of model parameters. The proposed ATMAD framework is validated on commonly-used compact models in academia and industry, showing its effectiveness for compact modeling for both I-V and C-V characteristics.

Advanced semiconductor lithography faces significant challenges as feature sizes continue to shrink, necessitating effective Multiple Patterning Layout Decomposition (MPLD) algorithms. Existing MPLD algorithms are inefficient or cannot support stitch insertion to achieve finer-grained optimal decom-position. This paper introduces an end-to-end GNN-based frame-work that not only achieves high-quality solutions quickly but also applies to layouts with stitches. Our framework treats layouts as heterogeneous graphs and performs inference through a message-passing mechanism. We deliver ultra-competitive, near-optimal solutions that are 10x faster than the exact algorithm (e.g., integer linear programming) and 3x faster than approximate algorithms (e.g., exact-cover, semi-definite programming).

Healthcare Education and Labeling for Cardiopulmonary Sounds, HEALSound, is an interactive platform designed to enhance the identification and labeling of adventitious cardiopulmonary sounds through gamification. HEALSound enables users, particularly medical professionals, to engage in exercises that improve their knowledge of abnormal heart and lung sounds while simultaneously contributing to the labeling of raw audio data. By incorporating real-time feedback and progress tracking, the app promotes continuous learning and provides a valuable crowdsourced resource for building high-quality labeled datasets over time. This dual-purpose platform not only aids in medical education but also contributes to the advancement of machine learning models for sound classification in healthcare. The system demonstrates a new potential for significant impact in educational and clinical environments by seamlessly integrating learning with data collection, ensuring scalability and the continuous improvement of cardiopulmonary sound databases.

Advances in digital stethoscopes and wearable health sensors now support real-time cardiopulmonary monitoring and AI-driven diagnostic tools. However, the extensive manual labeling required for large datasets of respiratory sounds presents a significant barrier, traditionally dependent on expert input. To address this, we introduce HEALSound, a mobile application designed to blend educational training with crowdsourced data labeling. By engaging users in interactive auscultation exercises and providing immediate feedback, HEALSound promotes skill development while generating high-quality labeled data through weighted consensus methods. Experimental results highlight the app’s dual effectiveness: enhancing diagnostic learning for users and accelerating the development of machine-learning models through enriched datasets, thus addressing critical challenges in AI-based health diagnostics.

Modeling lithography using machine learning is extremely data-intensive. Due to intellectual property privacy concerns and potential malicious attacks, design houses and foundries are unwilling to share their designs directly. To address the aforementioned concerns, we have proposed a personalized federated learning-based framework (pFed-Litho) to perform end-to-end lithography simulation. This framework incorporates a cross-level local training algorithm along with an integrated optimization method to generate personalized and local models, which overcome the generalization problem and slow convergence and oscillatory behavior in its loss function, respectively. The experimental results show that our pFed-Litho framework achieves up to 14.07% higher accuracy with reduced oscillatory behavior in the loss curve compared to the state-of-the-art works. Even with a dataset reduced by$100\times $, our framework maintains a stable accuracy of over 91%, representing a 50% increase compared to the U-Net model.

This paper presents a compact ring-oscillator (RO)-based phase-locked loop (PLL) implemented upon the principle that reference oversampling essentially boosts the reference frequency and thus extends the achievable bandwidth to such an extent that an area-efficient RO can be used without significantly sacrificing the phase noise (PN) and jitter performance when compared to conventional LC-based PLLs. By employing an analog reference oversampling PLL structure, RO noise is greatly suppressed by taking advantage of such an extended maximum PLL bandwidth. In conjunction with power- and spur-reduction techniques including a low-power time-multiplexed Gm stage and a capacitive parasitic-proof RO, this work implements a compact and low PN PLL without requiring complicated calibration or additional power/area penalties. Fabricated in a standard$0.18~\mu $m CMOS technology, the proposed PLL occupies an active area of 0.41 mm2. When operating at 1.6 GHz, the proposed PLL achieves an rms jitter of 585 fs with 5.7 mW power consumption, yielding a FoMREFof -240.1 dB.

A compact cost-effective Narrowband Internet-of-Things (NB-IoT) System-in-Package (SiP) in mass production is implemented in 55nm CMOS and Integrated Passive Device (IPD) process. The RF front-end components, i.e., inductors and capacitors, are integrated into an IPD die to reduce the Bill of Material (BOM) cost. Notably, the design eliminated the necessity of the antenna switches (ANTSW). On the IPD die, a diplexer is employed to separate the low-band (LB) and high-band (HB) paths, while in each band, the transmitter (TX) and the receiver (RX) share a common RF low pass filter through a co-matching network. To ensure robust performance, CMOS switches are placed at the PA’s drain and the LNA’s input, protecting the LNA core devices from breaking down and tuning essential impedance matching for both TX and RX. The built-in self-calibration scheme enables the chip to calibrate its TX/RX gain autonomously and flexibly, eliminating the use of external equipment therefore reducing the cost at the module production line. The NB-IoT SoC is integrated with the IPD die in a$7\times 7$QFN package. The system operates across the NB-IoT bands from 699MHz to 2200MHz (the CMOS chip supports 450MHz to 2200MHz), with transmitter’s Psatover +26dBm and achieving the HD2/HD3 below −36dBm when transmitting at +23dBm. The self-calibration scheme improves TX LO leakage and image by more than 15dB and ensures TX/RX gain accuracy within +/−0.5dB across the band and gain states.

Voltage reference circuits are crucial components within analog and mixed-signal integrated circuits, serving fundamental roles in maintaining stability and accuracy. Through examining bipolar circuits from both circuit and layout design viewpoints, we have introduced several new techniques to tackle challenges that were overlooked in previous studies. These techniques include 1) a Wilson current mirror structure, 2) a base current compensation resistor, 3) temperature-compensating resistors, 4) fuse trimming, 5) improved lateral PNP transistor design, and 6) a common-centroid layout for NPN transistors. The proposed circuit architecture is realized using a 1.5μm, 32V bipolar process. Measurement outcomes demonstrate that it achieves a temperature coefficient as low as 4.9ppm/∘C. Post-irradiation with a total dose of 500 krad (Si), the voltage reference exhibited a minimal variation of 0.10%, fulfilling the criteria for single-event latch-up resistance with a Linear Energy Transfer (LET) threshold exceeding 80.5 MeV⋅cm2/mg.

Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to near/subthreshold, achieving a sleep mode leakage power of 12.2 pW,$1.4\times $–$3.8\times $less than the prior CMOS DR-FFs. Our proposed DR-FFs consume the lowest active mode switching efficiency of 36.5 fJ/step,$1.2\times $–$4\times $less than the prior works, and a comparable transition efficiency of 1.9 fJ/step. Furthermore, our proposed DR-FFs require minimal control signals, logic gates, and switches, significantly reducing design complexity, and avoiding the drawbacks of nonvolatile data retention FFs (NV-FFs).

This work introduces an innovative wearable health-care system that offers personalized cardiopulmonary monitoring by continuously capturing a variety of physiological signals. Users can engage with the system to view their own data in real-time, thereby gaining a nuanced understanding of its multi-modal sensing capabilities and the potential for remote health monitoring.

Continuous physiological sound monitoring is crucial for the prevention, diagnosis, and treatment of various diseases like cardiopulmonary and gastrointestinal conditions. Wearable healthcare sensors have emerged as a potent solution, streamlining the capture, storage, transmission, and analysis of individualized physiological sounds. However, challenges exist including large data volumes, limited hardware computational capabilities, and constrained transmission bit rates. To address these issues, we propose a physiological sound compression system using compressive sensing with self-adaptive compression ratio across sound types to implement physiological sound compression and Optimized Discrete Cosine Transform (ODCT) reconstruction to reduce loss in effective bands. Evaluated on SPRSound and PhysioNet 2016, our approach attains correlation coefficients of 0.863 and 0.883 for respiratory and cardiac sounds, with -3.14 dB and -1.84 dB signal-to-noise ratio loss at 3.5 and 3.0 compression ratios. Implemented on a custom healthcare sensor, our approach optimizes bit rate to 1.73× and power consumption to 0.82× compared to the uncompressed system.

This paper presents a VCO-based ADC design for use in flexible electronics, specifically leveraging Low-Temperature Polysilicon Thin-Film Transistor (LTPS TFT) technology. The design achieves a resolution of 8.11 bits at a 20 MHz sampling rate with a bandwidth (BW) of 2.5kHz. A linearity compensation technique combining a resistive input stage with a frequency-dependent resistor (FDR)-based feedback loop significantly enhances the VCO linearity. Simulation results validate the design, exhibiting an R2value of 0.9999 for the VCO tuning curve, a Signal-to-Noise and Distortion Ratio (SNDR) of 50.57 dB, and a Spurious-Free Dynamic Range (SFDR) of 52.34 dB at a supply voltage of 10V. The proposed design also features the lowest Figure of Merit (FoM) (0.73 nJ/conversion-step) compared with the state-of-the-art.

In this paper, we demonstrate a bi-directional biomedical process-invariant pixel interface based on the LTPS-TFT that integrates a front-end amplifier, an analog-to-digital converter and a stimulator. The pixel interface can convert biopotential into digital signals. This near-sensor signal processing can avoid the interference of motion artifacts, and the all-digital transfer has a high noise tolerance. Under the process variation of 1×-1.4× threshold voltage and ±10% mobility fluctuations, the DC gain of the operational amplifier changes from 58.83 dB to 57.21 dB, and 39.09 dB to 37.88 dB for the front-end amplifier. Compared with the single-stage amplifier, the stability has been improved by 13.2×. The proposed pseudo differential VCO-based ADC can effectively eliminate second-order non-linearity which achieves the best performance in state-of-the-art TFT-ADCs. When the threshold voltage and mobility fluctuate, ENOB changes from 7.36 bit to 7.30 bit (OSR=64) and 11.52 bit to 11.14 bit (OSR=256). The change rate does not exceed 4%.

The fast-growing development in wearable electronic devices leads to high demand for small-volume, lightweight, and high-efficiency DC-DC power converters, particularly switched capacitor (SC) DC-DC converters. In this paper, we propose a synthesis framework of step-down SC DC-DC power converters to obtain an optimum converter topology under the design constraints of the conversion ratio and a minimum number of capacitors. The proposed rule-based clustering reduction techniques have reduced the search space and sped up the conversion ratio analysis. In the case study of 8:1 converter synthesis, the run-time for conversion ratio analysis is reduced by 1.26$\boldsymbol{\times}$$\boldsymbol{10^6}$. The proposed efficiency optimization method has improved the peak efficiencies of the cascaded 2:1 converter and Fibonacci converter by 4.7% and 12.8%. The proposed framework has identified new topologies and variants of conventional topologies. The variant of cascaded 2:1 converter shows an improvement of 8.2% on peak efficiency.

Process, voltage, and temperature (PVT) variations in chip fabrication or operation pose a significant challenge to the robustness of analog integrated circuits. Existing design techniques for mitigating PVT variations involve analyzing offsets of DC operating points, but this approach often leads to compromises in circuit performance. To address this challenge, we developed a ‘PVT-Transfer’ framework to facilitate knowledge transfer with evolutionary design. Specifically, by cross-operating the circuit parameters under variations, design knowledge is transferred through parameter migration, thus enhancing the robustness of the resultant circuit. In addition, we leverage data-driven learning to discover potential similarities among PVT variations, thereby mitigating negative knowledge transfer. The PVT-Transfer Framework is evaluated on three integrated voltage references and compared with four state-of-the-art circuit sizing methods. Based on post-layout Monte-Carlo simulations, this framework is verified to offer superior performance to existing methods, yielding a 60% reduction in power consumption, an 80% increase in temperature resilience, and up to 70$\times$enhancement in the figure of merit. Further, it leads to a 60% reduction in the number of required circuit simulations and is suitable for parallel computation.

Designing analog integrated circuits (ICs), particularly sensors and reference circuits, requires a significant amount of human expertise and time, largely due to the requirement of maintaining process, voltage, and temperature (PVT) consistency. So far, there has been plenty of work on tuning the circuit to meet the PVT consistency requirements by comparing the offset of the DC operating point, but this inevitably leads to circuit performance degradation. To improve, we propose a ‘PVT-Transfer’ framework that utilizes knowledge transfer among PVT corners through evolutionary multitasking. Specifically, via cross-operating the circuit parameters under different PVT corners, knowledge is transferred through parameter migration to improve the robustness of the circuit. Further, PVT-Transfer employs data-driven learning to identify potential similarities among PVT variations, thereby leading to more cost-effective optimization. This framework is evaluated on two voltage references and compared with four state-of-the-art circuit sizing methods. The post-layout Monte-Carlo simulation results verify that PVT-Transfer outperforms the existing methods. It reduces the number of simulations required by 60% compared to the GCN-RL method. Besides, PVT-transfer achieves up to 10× improvement in the figure of merit over the human design.

This paper presents a low-power, low-noise, gain and bandwidth individually tunable analog front-end (AFE) for ExG signals. The proposed three-stage AFE with a bandwidth programmable amplifier enables individually tuning the bandpass cutoff frequencies in the range of 0.4 to 1.9kHz as well as the gain from 40 to 63dB. Designed in a$0.35 \mu\mathrm{m}$CMOS process with an area of 0.3mm2, the AFE achieves over 120dB CMRR with input referred noise of 516nVrms and a noise efficiency factor of 2.57. The chip consumes$2.5 \mu\mathrm{A}$at 1.8V supply.

Conventional physics-based memristor device modeling methods highly rely on human expertise, which results in a long development period. To address the aforementioned challenges, we propose a new generalized memristor (GEM) device modeling framework based on the artificial neural network (ANN) technique, which has a minimum dependency on the underlying physics, resulting in a fast turn-around development time for customized memristor devices. GEM framework models the switching and conducting behaviors of the memristor devices separately, avoiding the signal-dependence issue in the prior time-series data modeling method. The result of the GEM framework is a compact model that supports general-purpose circuit simulators. Experimental results show that our compact model achieves a ratio of root-mean-square error to peak-to-peak (RMSE/PP) of 3.6% compared to the physics-based device model. Performance analysis of memristor-based logic and memristor crossbar circuits are conducted to demonstrate the effectiveness of our proposed GEM framework for the design and analysis of memristor-based circuits.

Malicious manipulation of very large-scale integration physical-layout design is a serious problem in modern integrated circuit design. The physical-layout design database requires a highly compressed secured storage medium. In this article, we propose a secured compressive asymmetrical convolutional auto-encoder (ACAE) machine learning framework, CompressKey, which performs layout compression and encryption simultaneously. It utilizes geometric features to eliminate redundancies in layout patterns. We propose a “Divide and Merge” technique to partition each layer into smaller sizes of unique patterns to address the inconsistency of layout pattern complexity. We also propose “Matrix Expansion” and “Matrix Reduction” techniques on the matrix-based pattern to achieve secured “near lossless” compression on the layouts. We have evaluated CompressKey on 14/28/32 nm open-source ICCAD contest databases and achieved a secured compression ratio of 4.54 with encryption features outperforming$1.22\times $–$1.59\times $compared to the state-of-the-art techniques.

The level shifter (LS) circuit has become an indispensable circuit component in both analog and digital systems. In the past decades, there has been an exponential increase in the academic publications for the LS circuits to improve their performances and their applications. Therefore, this review paper provides a comprehensive study of the LS circuit, ranging from circuit topologies and various design methodologies such as sizing methodology, layout design methodology, circuit evaluation methodology, and testing methodology. Finally, we evaluate the state-of-the-art LS circuits and present their performance metrics.

Performing chemical mechanical polishing (CMP) modeling for physical verification on an integrated circuit (IC) chip is vital to minimize its manufacturing yield loss. Traditional CMP models calculate post-CMP topography height of the IC’s layout based on physical principles and empirical experiments, which is computationally costly and time-consuming. In this work, we propose a CmpCNN framework based on convolutional neural networks (CNNs) with a transfer learning method to accelerate the CMP modeling process. It utilizes a multi-input strategy by feeding the binary image of layout and its density into our CNN-based model to extract features more efficiently. The transfer learning method is adopted to different CMP process parameters and different categories of circuits to further improve its prediction accuracy and convergence speed. Experimental results show that our CmpCNN framework achieves a competitive root mean square error ( RMSE ) of 2.7733Å with 1.89× reduction compared to the prior work, and a 57× speedup compared to the commercial CMP simulation tool.

An input-output regulated adaptive ramp ($\mathrm{IOR}^{2})$ for fast load transition of pulse width modulation (PWM) buck convertor is presented. The scheme employs an adaptive ramp regulated by input and the voltage from the error amplifier to achieve fast load response and low line and load regulation rate. Simulation shows that an under/overshoot voltage of −32 mV and 35 mV, with $8 \mu$ and $8.3 \mu \mathrm{s}$ recovery time are respectively obtained for the load current stepping between 1 A and 1.7 A. The line/load regulation rate is respectively $12.4 \mu \mathrm{V} / \mathrm{V}$ and $1.04 \mathrm{mV} / \mathbf{A}$. Implemented in a $0.25 \mu \mathrm{m}$ BCD process, the proposed IOR2PWM regulator is capable of converting input voltage of 5 V to 65 V to output range of 3.3 V to 60 V with adjustable switching frequency up to 2.2 MHz, showing a peak efficiency of 94.5% at 1 A load current.

The implementation of a power-efficient neuron array system with high throughput and controllable mismatch plays an important role in power-sensitive applications and brain simulations. This paper presents an array of 48 Integrate-and-Fire neurons with axon-sharing architecture implemented in 55-nm CMOS technology. The combination of log-domain circuits and comparator-sharing in neuron design achieves the integration of 3125 neurons/mm2and power consumption of 5.3 pJ/spike. The proposed time modulated axon-sharing synapse architecture realizes 5500 events/s/neuron unit throughput. A novel background calibration module is integrated to reduce the mismatch between neurons. Simulations presents a 45% improvement in SD of inter-spike interval variation. Finally, we validate the architecture by implementing a spiking neural network for solving a 3-stage Sudoku Puzzle. 100% success rate is obtained after calibration.

Brain machine interface systems will require recording thousands of neural channels in parallel to acquire large scale neuronal activity. High bandwidth action potential signal will overload the data communication bandwidth, and on-site spike sorting can extract essential information, however, requires extensive computational resources to achieve high classification accuracy. This demands for high resources consuming, especially in large-scale real-time sorting systems. In this work, a customized unsupervised training engine incorporated with distributed and optimized sorting channels is presented in order to reduce the hardware complexity without compromising the accuracy of spike sorting. A mixed-domain feature set is extracted in each channel, followed by feature based sorting. Each channel will constantly monitor the sorting accuracy and will request training engine intervention when in need. The proposed system is implemented in a 180 nm CMOS process, consuming only 0.33 μ W/channel with a clock of 25 kHz and power supply of 1.8 V, and in-channel sorting occupies 0.0023 mm2, with training engines occupying 1.956 mm2, which can be shared by all the channels.

The design and verification of memristor crossbar circuits and systems demand computationally efficient models. The conventional device-level memristor model with a circuit simulator such as simulation program with integrated circuit emphasis (SPICE) to solve a memristor crossbar is time exhaustive. Hence, we propose a neural network-based memristor crossbar modeling method, XBarNet. By transforming memristor crossbar modeling to pixel-to-pixel regression, XBarNet avoids the iterative procedure in the conventional SPICE method, accelerating the runtime significantly. Meanwhile, XBarNet models the interconnect resistance and nonlinear$I-V$effect of memristor crossbars, which minimizes the simulation errors. We first propose a feature extraction method to bridge a memristor crossbar circuit and a neural network. Then, the network based on the convolutional autoencoder architecture is developed and the filter pruning technique is applied onto XBarNet to reduce the runtime computational cost. The experimental result shows our proposed XBarNet achieves over$78\times $runtime speed up and$1.7\times $memory reduction with only 0.28% relative error comparing to the SPICE simulator.

This paper presents a multi-rate hybrid multistage noise shaping (MASH) ΔΣ modulator (DSM) with high tolerance to noise leakage. The front-end discrete-time (DT) stage works in a low sampling frequency while the back-end continuous-time (CT) stage runs in a 4X higher clock frequency. Thereby, the quantization noise of the first stage could be easily extracted by using feedforward topology. Moreover, the required upsampling behavior between the two stages is intrinsically implemented in the CT second stage without requiring an additional 4X upsampler. This multi-rate hybrid DT/CT DSM combines the accurate feature of DT loop filter and the high-speed advantage of CT loop filter. Eventually, it results in a high-speed operation for wideband applications while exhibiting a much higher tolerance to noise leakage compared to a conventional CT MASH structure. Simulations results demonstrate the efficacy of the proposed architecture.

Circuits based on tunneling FET (TFET) devices are fueling the beyond CMOS logic design, meeting the ultra-low-power demands for Internet-of-Things (IoT) applications. This paper presents a highly energy-efficient hybrid TFET/FinFET level shifter (LS) circuit, providing a robust signal up-conversion from deep subthreshold voltage. A pulse-triggered dynamic fully-regenerative latch and two modified dynamic current generators are incorporated to overcome the timing variation of input differential signals and current contention in the cross-coupled circuit. The simulation results show that the hybrid TFET/FinFET LS circuit has achieved a low propagation delay, dynamic power consumption, and power-delay-product (PDP) of ≤378 ps, ≤39.6 μW, and ≤13,950 ns-nW, respectively while converting the input signal from the ultra-low-voltage of sub-50mV to the nominal supply voltage of FinFET (0.8-1.2V). The proposed architecture has achieved up to 2.71-to-15.99x improvement in PDP compared to the reported state-of-the-art LS architectures.

With Moore's law reaching its limits, the use of new materials or new devices' structure has emerged as the next generation of CMOS devices. Among all, tunneling field-effect transistors (TFETs) have achieved a steep sub-threshold slope of less than 60mV/decade yet there is a lack of a complete process design kit (PDK) for large-scale circuit design. Hence, we present an open-source 15nm TFET PDK (15nmTFETPDK), which is based on FreePDK15 with additional support for open-source TFET models and its associated Cadence Virtuoso pcell in OA format and Mentor Calibre physical verification files. Our users can design their circuit in the Cadence Virtuoso platform and verify the consistency of the drawn layout and the circuit through the Calibre Platform. We hope that this open-source PDK allows them to further advance their research with new emerging devices.

A configurable metal-oxide-metal (MOM) capacitor structure is highly desirable for the diversified electronics market. Based on the analytical study on different sources of capacitance in MOM capacitors, and understandings of how the lithography process impacts the final shape of the capacitors, we proposed a highly configurable and extensible spiral based capacitor. Several forms of spiral capacitors have been generated and performed lithography simulation to obtain accurate capacitance value. Compared with the single-layer interdigital MOM capacitor, The proposed spiral based capacitors has been configured to achieve a 1.23× higher capacitance density than a MOM capacitor or the smallest variation among all structures.

Functional near-infrared spectroscopy (fNIRS) is considered as a non-invasive and effective brain-computer interface technology. Wearable high-resolution fNIRS requires a large-scale LED array, which consumes a lot of power, and shorten the battery life. This paper proposes a spatial adaptive sampling (SAS) method that can take advantage of the spatial sparsity of fNIRS devices and greatly reduce the power consumption while maintaining high image quality. To improve the performance of the proposed SAS technique, a low power binary neural network (BNN) is proposed to accurately predict the current brain task. And the optimal dynamic LED pattern for each brain task is investigated. The proposed SAS technique is validate through an off-line experiment, it can reduce the power consumption of the LED array by 62.5% compared to not using SAS technology while maintaining a PSNR (Peak Signal to Noise Ratio) of 33 dB.

Level converting is increasingly difficult in ultra-low voltage circuits with the aggressive scaling down of the input voltage. In this paper, we proposed a wide output range level shifter (LS) with the ultra-low input voltage. The proposed LS is integrated with a positive flip-flop function with a three-phase time borrowing scheme at the sampling edge. The working principle eliminates the current contention problem in the conventional cross-coupled level shifters, which allows a much higher output range at ultra-low input. The time borrowing technique also allows a relaxed timing constraint, which increases the timing margin and improves robustness against variation in ultra-low voltage circuits. The proposed LS is implemented with 45nm CMOS technology. Simulation results show that the proposed structure achieves a propagation delay of 10.01ns, power consumption of 11.23pW, and a power-delay-product (PDP) of 112,412ns-nW when converting an input signal of 200mV to an output level of 3 V.

Wearable Artificial Intelligence-of-Things (AIoT) devices demand smart gadgets that are both resource and energy-efficient. In this paper, we explore efficient implementation of binary convolutional neural network employing function merging and block reuse techniques. The hardware implemented in field programmable gate array (FPGA) platform can classify ventricular beat in electrocardiogram achieving accuracy of 97.5%, sensitivity of 85.7%, specificity of 99.0%, precision of 92.3%, and F1-score of 88.9% while consuming only 10.5-μW of dynamic power dissipation.

In this paper, we proposed a resource-efficient 'QRS' detector with superior detection accuracy. Inspired by the strategy of the folded architecture, we adopted a reconfigurable time-sharing computation unit with a pipeline schedule. To further precisely locate the position of the 'R' peak and minimize the extra hardware cost, we designed the position calibration unit (PCU) based on the data compression technique. The proposed architecture was implemented on Xilinx Zynq-7000 with Verilog programming language. The proposed architecture achieves a sensitivity, Se of 99.76%, a precision, +P of 99.85%, and a detection error rate, DER of 0.40% on MIT-BIH database, which attains the best performance compared to state-of-the-art designs. Furthermore, the proposed architecture achieves a better hardware efficiency with 13×, 1.28×, and 4.35× reductions in computing resources, storage memory, and power consumption, respectively.

The advancement of object detection algorithms makes them widely used in autonomous systems. However, due to high computational complexity of Convolutional Neural Networks(CNN), stringent latency requirement is hard to meet for real-time object detection. To address this problem, a low-latency accelerator architecture is proposed in this paper. A fine-grained column-based pipeline architecture with padding skip technique is implemented to reduce the start-up time of pipeline. In order to cut down the computational time of CNN, double signed-multiplication correcting circuit is introduced. In addition, pooling unit with share buffer is proposed to reduce storage cost for pooling layer. To demonstrate our new architecture, we implement the YOLOv2-tiny deep neural network (you-only-look-once) with input size 1280×384 on ZC706 development board, improving the latency by 2.125× to 2.34× compared to previous FPGA accelerator for YOLOv2-tiny.

The conventional mapping method between RRAM array and convolutional weights faces two key challenges: 1) nonoptimal energy efficiency and 2) RRAM's temporal variation. To address these challenges, we propose shift and duplicate kernel (SDK) convolutional weight mapping architecture. Each kernel is duplicated multiple times and rearranged on different bitlines in a shifted manner, enabling higher intralayer computational parallelism, and reducing the number of input data loading. Hence, this architecture reduces the computational latency and energy consumption in both forward and backward propagation phases. Furthermore, we have introduced a parallel-window size allocation algorithm and a kernel synchronization method. Our proposed parallel-window size allocation algorithm aims to balance the interlayer pipeline architecture, thus improving the overall energy efficiency and area efficiency. Our proposed kernel synchronization method uses an averaging method to suppress the effect of temporal variation during weight update, enhancing the system's robustness for training. From our experiment results, our proposed architecture achieves ~6.8× area efficiency and ~2.1× energy efficiency over the conventional interlayer pipeline architecture. Significant improvement in classification accuracy by 21.7% under a temporal variation of 1%-5% is achieved during on-chip training task on the Cifar-10 dataset.

The use of deep neural networks in pattern matching has tremendously improved the accuracy of the lithographic hotspot detection, preventing any catastrophic chip failure. In this paper, we propose three data augmentation techniques ("Translation", "Gaussian noise", and "Fill shapes") to deal with the imbalance outlier lithographic hotspot problem and adopt the neural ordinary differential equations networks (Litho-NeuralODE) to improve the detection accuracy. Our architecture uses 28x28 pixel clips to perform the hotspot classification. Experimental result on ICCAD 2012 Contest benchmarks shows that our proposed framework achieves the overall highest accuracy of 98.7% and the lowest misses of 10 on average, outperforming the state-of-the-art works.

Implantable medical microsystems need an efficient power and data transmission link. The demand for increasing the battery life requests for higher power transfer efficiency (PTE), whereas the increasing functionality of the implantable chip demands a higher data-rate. The traditional single-pair-of-coil link based on Amplitude-Shift keying (ASK) modulated Class-E amplifier tends to have limited immunity on the interference. In addition, due to the conflict on the quality factor (Q) between the power transmission and data transmission band, high PTE and high data rates are difficult to achieve at the same time. This paper proposes a power and data transmission link based on the adaptive duty-cycling binary phase-shift keying (BPSK) modulated Class-E amplifier. The Class-E works alternatively between two modes determined by two clocks with different duty-cycles. The variation of the duty-cycle modulates the phase of the carrier through the resonant networks of the Class-E amplifier. A low-power Costas Loop is adopted to efficiently synchronize the carrier and recover the data from an inductive received signal. The whole link has been implemented and simulated in a 350-nm CMOS process. The simulation shows under date-rate of 4 Mbps, the link achieves a PTE of 53% with an energy efficiency of 600 pJ/bit.

High-resolution analog signal conditioning or processing circuit requires careful design of building blocks to minimize any circuit non-idealities due to the manufacturing process and operating conditions. In this paper, we present a highly precise analog subtractor circuit with several background calibration techniques. This circuit is designed and can be further developed for the capacitive-based successive subtraction ADC circuit. Our proposed calibration method is based on a capacitive-array of 15 unary-weighted unit capacitors, which compensates errors due to the amplifier's voltage offset and capacitors' mismatches and parasitic capacitance. The circuit is implemented using 45nm CMOS technology, and the power consumption is 82.8μW. It operates at a frequency of 166.7kHz, corresponding to 6μs per operation. With our calibration method, we have reduced the average percentage error from 3.99% to 0.457% across the entire dynamic range, and with the worst-case error of 700μV.

Physical Unclonable Function (PUF) circuit extracts information from variations in a circuit or physical design to generate a unique key for electronics authentication, such as IoT devices and embedded systems. We proposed a high-speed pseudo linear feedback shift register with multiple ring oscillators PUF (PL-MRO-PUF), replacing the registers in LFSR with combinational logic to resemble a delay-sensitive ring oscillator (RO) circuit Furthermore, the use of multiple LFSR-based ROs with each different number of stages to form a 128-bit PUF allows us to increase the output's entropy and throughput. Hence, we have implemented the architecture in the Xilinx Artix-7 FPGA series boards. We have improved the operating frequency by 1.95×, and improve FoM by 1.5× compared to the PL-PUF [1]. We also have achieved higher randomness and uniqueness of 98.8% and 51.7%, respectively, compared to the conventional Arbiter PUF (A-PUF) [2].

In this demonstration, we present a non-invasive, real-time lung imaging system based on the electrical impedance tomography (EIT) technique. EIT is a medical imaging technique based on the electrical properties, i.e. resistivity and permittivity of tissues and organs. This demo is based on an EIT system-on-chip that utilizes frequency division multiplexing scheme to improve the throughput by 10, allowing clinicians to identify and prevent mechanical pulmonary injury during lung ventilation.

In this paper, we proposed an improved true random number generator (TRNG), which comprises a low-bias hardware random number generator (HRNG) and a scrambler based on linear-feedback shift register (LFSR). The HRNG reduces both DC offset from the noise sources and offset voltage from the comparator to generate low-bias bitstream. The LFSR-based scrambler further reduces the bias to zero without sacrificing the throughput rate. Randomness quality is verified by Monte Carlo simulations using the randomness test suite.

The overall accuracy and linearity of a matching-limited successive-approximation-register analog-to-digital converter are primarily determined by its digital-to-analog converter's (DAC's) matching characteristics. As the resolution of the DAC increases, it is harder to achieve accurate capacitance ratios in the layout, which are affected by systematic and random mismatches. An ideal placement for the DAC array should try to minimize the systematic mismatches, followed by the random mismatch. This paper proposes a placement strategy, which incorporates a matrix-adjustment method for the DAC, and different placement techniques and weighting methods for the placements of active and dummy unit capacitors. The resulting placement addresses both systematic and random mismatches. We consider the following four systematic mismatches such as the first-order process gradients, the second-order lithographic errors, the proximity effects, the wiring complexity, and the asymmetrical fringing parasitics. The experimental results show that the placement strategy achieves smaller capacitance ratio mismatch and shorter computational runtime than those of existing works.