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Abde Ali Kagalwalla

dblp:93/8857 · DBLP profile ↗
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6ranked-venue papers
4as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 4 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design
0.632017
Benchmarking of Mask Fracturing Heuristics · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Effective model-based mask fracturing for mask cost reduction · DAC 2015
Design-Aware Mask Inspection · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Electronic design automation › physical design › optical proximity correction
inverse lithography technology
0.522017
Benchmarking of Mask Fracturing Heuristics · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Effective model-based mask fracturing for mask cost reduction · DAC 2015
Electronic design automation › physical design
mask optimization
0.522017
Benchmarking of Mask Fracturing Heuristics · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Effective model-based mask fracturing for mask cost reduction · DAC 2015
Electronic design automation
design for manufacturability
0.212015
Effective model-based mask fracturing for mask cost reduction · DAC 2015
Electronic design automation › physical design
lithography
0.212015
Effective model-based mask fracturing for mask cost reduction · DAC 2015
Electronic design automation
yield analysis
0.112012
Design-Aware Mask Inspection · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Electronic design automation › physical design
optical proximity correction
0.012012
Design-Aware Mask Inspection · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012

Methods — techniques the papers use, named apart from their topics

integer linear programming · 0.3branch-and-price · 0.3benchmark generation · 0.3overlapping shots · 0.2e-beam proximity effect compensation · 0.2defect criticality analysis · 0.1analytical modeling · 0.1
YearPublicationVenuePosition
2017 Benchmarking of Mask Fracturing Heuristics
abstract
Aggressive resolution enhancement techniques such as inverse lithography (ILT) often lead to complex, nonrectilinear mask shapes which make mask writing extremely slow and expensive. To reduce shot count of complex mask shapes, mask writers allow overlapping shots, due to which the problem of fracturing mask shapes with minimum shot count is NP-hard. The need to account for e-beam proximity effect makes mask fracturing even more challenging. Although a number of fracturing heuristics have been proposed, there has been no systematic study to analyze the quality of their solutions. In this paper, we first propose a method to generate tight upper and lower bounds for actual ILT mask shapes by formulating mask fracturing as an integer linear program and solving it using branch and price. Since the integer program requires significant computational resources to compute reasonable bounds, we propose a new method to generate benchmarks with known optimal solutions, that can be used to evaluate the suboptimality of mask fracturing heuristics. To make the generated benchmark shapes realistic, we further propose a novel automated benchmark generation method that takes any ILT shape as input and returns a benchmark shape which looks similar to the input shape and for which the optimal fracturing solution is known. Using these methods, we compare the suboptimality of four mask fracturing heuristics. Our results show that even a state-of-the-art prototype (version of) capability within a commercial EDA tool for e-beam mask shot decomposition can be suboptimal by as much as 2.6× for real ILT shapes and by 6.0× for generated benchmarks.
Tuck-Boon Chan, Puneet Gupta 0001, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4
2015 Effective model-based mask fracturing for mask cost reduction
abstract
The use of aggressive resolution enhancement techniques like multiple patterning and inverse lithography (ILT) has led to expensive photomasks. Growing mask write time has been a key reason for the cost increase. Moreover, due to scaling, e-beam proximity effects can no longer be ignored. Model-based mask fracturing has emerged as a useful technique to address these critical challenges by allowing overlapping shots and compensating for proximity effects during fracturing itself. However, it has been shown recently that heuristics for model-based mask fracturing can be suboptimal by more than 1:6x on average for ten real ILT shapes, highlighting the need for better heuristics. In this work, we propose a new model-based mask fracturing method that significantly outperforms all the previously reported heuristics. The number of e-beam shots of our method is 23% less than a state-of-the-art prototype version of capability within a commercial EDA tool for e-beam mask shot decomposition (PROTO-EDA) for ten ILT mask shapes. Moreover, our method has an average runtime of less than 1:4s per shape.
Abde Ali Kagalwalla, Puneet Gupta 0001
DAC1
2014 EUV-CDA: Pattern shift aware critical density analysis for EUV mask layouts
abstract
Despite the use of mask defect avoidance and mitigation techniques, finding a usable defective mask blank remains a challenge for Extreme Ultraviolet Lithography (EUVL) at sub-10nm node due to dense layouts and low CD tolerance. In this work, we propose a pattern shift-aware metric called critical density, which can quickly evaluate the robustness of EUV layouts to mask defects (300-1300x faster than Monte Carlo, with average mask yield root mean square error (RMSE) ranging from 0.08%-6.44%), thereby enabling design-level mask defect mitigation techniques. Our experimental results indicate that reducing layout regularity improves the ability of layouts to tolerate mask defects via pattern shift.
Abde Ali Kagalwalla, Michale Lam, Kostas Adam, Puneet Gupta 0001
ASP-DAC1
2014 Benchmarking of mask fracturing heuristics
abstract
Aggressive resolution enhancement techniques such as inverse lithography (ILT) often lead to complex, non-rectilinear mask shapes which make mask writing extremely slow and expensive. To reduce shot count of complex mask shapes, mask writers allow overlapping shots, due to which the problem of fracturing mask shapes with minimum shot count is NP-hard. The need to correct for e-beam proximity effect makes mask fracturing even more challenging. Although a number of fracturing heuristics have been proposed, there has been no systematic study to analyze the quality of their solutions. In this work, we propose a new method to generate benchmarks with known optimal solutions that can be used to evaluate the suboptimality of mask fracturing heuristics. We also propose a method to generate tight upper and lower bounds for actual ILT mask shapes by formulating mask fracturing as an integer linear program and solving it using branch and price. Our results show that a state-of-the-art prototype [version of] capability within a commercial EDA tool for e-beam mask shot decomposition can be suboptimal by as much as 3.7× for generated benchmarks, and by as much as 3.6× for actual ILT shapes.
Tuck-Boon Chan, Puneet Gupta 0001, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng, Emile Sahouria
ICCAD4
2012 Design-Aware Mask Inspection
abstract
Mask inspection has become a major bottleneck in the manufacturing flow taking up as much as 40% of the total mask manufacturing time. In this paper, we explore techniques to improve the reticle inspection flow by increasing its design awareness. We develop an algorithm to locate nonfunctional features in a postoptical proximity correction layout without using any design information. Using this, and the timing information of the design (if available), the smallest defect size that could cause the design to fail is assigned to each reticle feature. The criticality of various reticle features is then used to partition the reticle such that each partition is inspected at a different pixel size and sensitivity so that the false and nuisance defect count is reduced without missing any critical defect. We also develop an analytical model to estimate the false and nuisance defect count. Using those models, our simulation results show that this design-aware mask inspection can reduce the false and nuisance defect count for a critical polysilicon layer from 80 defects down to 49 defects, leading to substantial reduction in defect review load. We also develop a model to estimate first pass yield (FPY) and show that our method can improve the FPY for a polysilicon layer from 11% to 30%. Apart from the polysilicon layer, the potential benefit of this approach is analyzed for active, contact and all the metal/via layers.
Abde Ali Kagalwalla, Puneet Gupta 0001, Christopher J. Progler, Steve McDonald
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2010 Design-aware mask inspection
abstract
Mask inspection has become a major bottleneck in the manufacturing flow taking up as much as 30% of the total manufacturing time. In this work we explore techniques to improve the reticle inspection flow by increasing its design awareness. We develop an algorithm to locate non-functional features in a post-OPC layout with 100% accuracy without using any design information. Using this, and timing information of the design (if available), we assign a minimum size defect to each reticle feature that could cause the design to fail. The criticality of various reticle features is then used to partition the reticle such that each partition is inspected at a different pixel size and sensitivity so that the false+nuisance defect count is reduced without missing any critical defect. Up to 4X improvement in false+nuisance defect count is observed with our technique resulting in up to 55% improvement in first pass yield coming from reduction in nuisance defects and substantial reduction in defect review load.
Abde Ali Kagalwalla, Puneet Gupta 0001, Christopher J. Progler, Steve McDonald
ICCAD1