The threat of hardware reverse engineering is a growing concern for a large number of applications. A main defense strategy against reverse engineering is hardware obfuscation. In this paper, we investigate physical obfuscation techniques, which perform alterations of circuit elements that are difficult or impossible for an adversary to observe. The examples of such stealthy manipulations are changes in the doping concentrations or dielectric manipulations. An attacker will, thus, extract a netlist, which does not correspond to the logic function of the device-under-attack. This approach of camouflaging has garnered recent attention in the literature. In this paper, we expound on this promising direction to conduct a systematic end-to-end study of the VLSI design process to find multiple ways to obfuscate a circuit for hardware security. This paper makes three major contributions. First, we provide a categorization of the available physical obfuscation techniques as it pertains to various design stages. There is a large and multidimensional design space for introducing obfuscated elements and mechanisms, and the proposed taxonomy is helpful for a systematic treatment. Second, we provide a review of the methods that have been proposed or in use. Third, we present recent and new device and logic-level techniques for design obfuscation. For each technique considered, we discuss feasibility of the approach and assess likelihood of its detection. Then we turn our focus to open research questions, and conclude with suggestions for future research directions.

Recent research on low power circuits make use of dual VT and strained silicon technologies. Low VT assignment on performance critical paths improves performance at the expense of leakage current. Strained silicon devices on the other hand have greater leakage but provide much larger ON current. The increased drive strength can be used to reduce gate sizes. In this work we show that selective use of strained silicon gates in high-activity critical paths reduce overall power due to decreased dynamic power arising from smaller gate sizes, that more than offset increased leakage due to strained silicon gate. Similarly, we find that up-sizing gates in low-activity critical paths reduce total power. Even though up-sized gates dissipate more dynamic power, lower switching activity, coupled with lower leakage compared to low VT devices make this a better choice. An optimization algorithm based on slack distribution between low and high switching activity gates is presented. Simulation results show an overall power benefit of 5.4% while improving performance by 15% even though overall leakage is 1% higher than original circuit.