Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
EDBT 2026 Demo / reviewers in the wild / expert

Charlotte Metzger

dblp:94/1078 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
functional verification		 0.011995
Test Program Generation for Functional Verification of PowerPC Processors in IBM · DAC 1995
Electronic design automation
hardware verification and test		 0.011995
Test Program Generation for Functional Verification of PowerPC Processors in IBM · DAC 1995
Electronic design automation › hardware verification and test
processor verification		 0.011995
Test Program Generation for Functional Verification of PowerPC Processors in IBM · DAC 1995
Electronic design automation › hardware verification and test › test generation › test case generation
test program generation		 0.011995
Test Program Generation for Functional Verification of PowerPC Processors in IBM · DAC 1995

Methods — techniques the papers use, named apart from their topics

heuristic testing · 0.0
YearPublicationVenuePosition
1995 Test Program Generation for Functional Verification of PowerPC Processors in IBM
abstract
A new methodology and test program generator have been used for the functional verification of six IBM PowerPC processors. The generator contains a formal model of the PowerPC architecture and a heuristic data-base of testing expertise. It has been used on daily basis for two years by about a hundred designers and testing engineers in four IBM sites. The new methodology reduced significantly the functional verification period and time to market of the PowerPC processors. Despite the complexity of the PowerPC architecture, the three processors verified so far had fully functional first silicon. 1 Introduction A new methodology and tool for functional test program generation has been used for several IBM PowerPC processors. The functional verification period and the processors time to market were reduced. Only one fifth of the simulation cycles needed to verify a RISC System/6000 processor with a previous generator was needed with the new methodology for a PowerPC processor. The new g...
Aharon Aharon, Dave Goodman, Moshe Levinger, Yossi Lichtenstein, Yossi Malka, Charlotte Metzger, Moshe Molcho, Gil Shurek
 DAC6