This paper presents a system-on-chip (SoC) architecture for an active implantable microsystem that combines electrical recording with optogenetic stimulation for closed-loop neuromodulation. The SoC is designed to support a 4-shank optrode (opto-electrode) fork with 8 differential recording channels (0.1-5000Hz bandwidth, 10mVpp range, 12-bit resolution) to observe neural signals on electrodes and 32 driver circuits (2mA range, 6-bit current resolution with μs timing resolution) for microLED optical stimulation. Each SoC additionally integrates diagnostic instrumentation to measure electrical resistance across any of its I/O lines. The SoC features a custom 4-wire interface that provides power and data communication across multiple chips using a shared bus allowing for multiple forks to be stacked to form two dimensional optrode arrays. Each chip has an independent controller that receives, interprets and executes commands, and can transmit neural data while simultaneously controlling LED outputs. The circuit is implemented in a 180nm CMOS process, with each chip occupying a 5mm×2.45mm silicon footprint, designed specifically to mount on the base of the silicon optrode fork.

As the demand for high channel counts and high-resolution recordings of neural activity continues to grow, the increased power and data rate generated impose hard constraints on the telemetry capabilities of wireless implantable neural interfaces. To address this challenge, this work presents a novel system architecture for a reconfigurable readout circuit. It provides per-channel data rate reduction and adaptable bandwidth to match the characteristics and evolution of the neural signals under non-ideal electrode-tissue interactions. The system consists of a 14-bit hybrid continuous-time/discrete-time delta-sigma (CT/DT-∆Σ) analog front-end (AFE) followed by event-based decimation (EBD) which exploits the inherent sparsity in neural signals. The proposed AFE and EBD co-design was simulated using artifact-laden nonhuman primate microwire recordings. Results demonstrate a dynamic range of 76 dB, ensuring artifact robustness, along with up to a two-order-of-magnitude reduction in output data rate and power-area decimation footprint per channel, offering flexibility for high-quality (14 dB NRMSE) and medium-quality (8 dB NRMSE) reconstructions, based on the characteristics of the neural signals recorded at each channel.

This paper presents a programmable current source circuit aimed at neuromodulation applications capable of achieving a peak efficiency of 98 % during the stimulation phase. It also offers a high voltage compliance almost 10 V. The circuit is based on our previous work that leverages a small drain-source voltage of transistors working in the triode region to improve the efficiency. The circuit was designed in a commercially-available 180 nm HV CMOS technology. The circuit area is 0.021 mm2. The circuit achieves a minimum operating output voltage of just 17 mV.

Emerging resistive technologies include several nonlinear devices with the capability of changing their resistive state based on the voltage (/current) across (/flowing through) the device. The state of these devices is typically read by applying a small DC voltage across the DUT and measuring the current flowing through it (or vice-versa). However, given their non-linear behaviour, a change in voltage across the device, albeit small, will result in a change in the measured resistance. This is undesirable when characterising these devices, as voltage drops due to metal routing or switches in the signal path will affect the measured resistance. This work puts forward the idea of closing the loop by sensing the voltage across the DUT through a Kelvin connection, and then making adjustments to the line voltage to compensate for any voltage drop. This in turn enables larger arrays, and a higher number of states to be read because of the increased precision. An on-chip CMOS design is proposed through the use of a dual-input-pair amplifier. The resulting system is capable of driving a load between 1 kΩ and 10 MΩ with a settling time less than 1 µs for a DUT read voltage of 0.5 V.

Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device’s resistance range to be between 1k$\Omega$ and 10M$\Omega$ with a minimum voltage range of ±1.5V on the device.

A number of recent and current efforts in brain machine interfaces are developing millimetre-sized wireless implants that achieve scalability in the number of recording channels by deploying a distributed 'swarm' of devices. This trend poses two key challenges for the wireless power transfer: (1) the system as a whole needs to provide sufficient power to all devices regardless of their position and orientation; (2) each device needs to maintain a stable supply voltage autonomously. This work proposes two novel strategies towards addressing these challenges: a scalable resonator array to enhance inductive networks; and a self-regulated power management circuit for use in each independent mm-scale wireless device. The proposed passive 2-tier resonant array is shown to achieve an 13.5% average power transfer efficiency, with ultra-low variability of 1.77% across the network. The self-regulated power management unit then monitors and autonomously adjusts the supply voltage of each device to lie in the range between 1.7V-1.9V, providing both low-voltage and over-voltage protection.

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.

“Fail often to succeed sooner” is a common mantra that we are told is the secret to success. When reporting research results, however, scholars rarely write about their failed attempts and only focus on the successful ones. Perhaps the source of this disconnect between what we preach and what we do can be found in the underlying assumption that published work is meant to move the field forward and failed attempts supposedly do not. The goal of the confessions presented in this paper is to show that even failed attempts are genuine and valuable contributions to our field provided that we learn from our mistakes and correct them. The 27 confessions span from planning oversights, digital and analog design errors, misunderstanding of devices, overlooked parasitics, LVS errors, and troubles in testing.

Here we report on a novel optoelectronic architecture capable to add in-phase the current pulses generated by each one of the fast Si photodiodes forming an array illuminated by laser pulses. The aim is to increase the total photodiode sensitive area to achieve higher output pulsed current values by maintaining unaltered the response time, the bandwidth and the reverse bias voltage proper of each single photodiode. This result is important for many modern applications in biophysics and biomedicine like the brain machine interfaces, that require real time evaluation of environmental/sample changes through the acquisition of signals at high data rates under high signal-to-noise ratio conditions. As a consequence, these applications use sub-nanosecond laser pulses that are revealed by large bandwidth photodiodes having small sensitive area to attain low values of the internal junction capacitance. Thus, any small optical misalignment between the laser beam and the photodiode sensitive area in transcutaneous optical biotelemetry strongly decreases the system detection efficiency and performances. The proposed optoelectronic system resolves this problem being capable to sum in-phase the current pulses generated by each one of the photodiodes forming the array into a single current pulse maintaining the condition of fast response in terms of rise and fall times and bandwidth. This solution employs a Kirchhoff node to sum the different photocurrents, a decoupling current buffer and a transimpedance amplifier to amplify the current pulses summed at the node. We investigated the performances of the optoelectronic system by using photodiodes with different sensitive areas and junction capacitances (i.e., different bandwidths and rise and fall times) for laser pulses repetition rates up to 200 MHz. We also experimentally characterized the circuitry composed by an array of 4 fast photodiodes by using 800 ps laser pulses at a repetition rate of 200 MHz proving that the achieved response times and bandwidth remain the same of those ones of each single photodiode. Moreover, we demonstrated that the maximum value (i.e., the peak) of the obtained output current pulses is multiplied by a factor 4, i.e., equal to the number of the photodiodes forming the array having an overall sensitive area enhanced by the same factor.

Deep brain stimulation (DBS) for Parkinson's disease, essential tremor and epilepsy is an established palliative treatment. DBS uses electrical neuromodulation to suppress symptoms. Most current systems provide a continuous pattern of fixed stimulation, with clinical follow-ups to refine settings constrained to normal office hours. An issue with this management strategy is that the impact of stimulation on circadian, i.e. sleep-wake, rhythms is not fully considered; either in the device design or in the clinical follow-up. Since devices can be implanted in brain targets that couple into the reticular activating network, impact on wakefulness and sleep can be significant. This issue will likely grow as new targets are explored, with the potential to create entraining signals that are uncoupled from environmental influences. To address this issue, we have designed a new brain-machine-interface for DBS that combines a slow-adaptive circadian-based stimulation pattern with a fast-acting pathway for responsive stimulation, demonstrated here for seizure management. In preparation for first-in-human research trials to explore the utility of multi-timescale automated adaptive algorithms, design and prototyping was carried out in line with ISO risk management standards, ensuring patient safety. The ultimate aim is to account for chronobiology within the algorithms embedded in brain-machine-interfaces and in neuromodulation technology more broadly.

This paper presents a novel analogue to digital converter using an oscillator-based loop filter for high-dynamic range bio-sensing applications. This is the first third-order feedforward ΔΣ modulator that strictly uses time domain integration for quantisation noise shaping. Furthermore we propose a new asynchronous extended-phase detection technique that increases the resolution of the 4 bit phase quantiser by another 5 bits to significantly improve both dynamic range and reduce the noise-shaping requirements. Preliminary simulation results show that this type of loop-filter can virtually prevent integrator saturation and achieves a peak 88 dB SNDR for kHz signals. The proposed system has been implemented using a 180 nm CMOS technology occupying 0.102 mm2and consumes 13.7 μW of power to digitise the 15 kHz signal bandwidth using a 2 MHz sampling clock.

This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noise-shaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB. We propose a novel fully-capacitive topology which allows for high-speed asynchronous conversion together with a background calibration scheme to reduce the oversampling requirement by 10× compared to prior-art. A 0.18μm CMOS technology is used to demonstrate preliminary simulation results together with analytic measures that optimise parameter and topology selection. The proposed system is able to achieve a FoMSof 183 dB for a maximum signal bandwidth of 15.6 kHz while dissipating 68 μW from a 1.8 V supply. A peak SNDR of 102 dB is demonstrated for this rate with a 0.201 mm2area requirement.

This paper presents a 32×32 ISFET sensing array with in-pixel digitisation for pH sensing. The in-pixel digitisation is achieved using an inverter-based sensing pixel that is controlled by a triangular waveform. This converts the pH response of the ISFET into a time-domain signal whilst also increasing dynamic range and thus the ability to tolerate sensor offset. The pixels are interfaced to a 15-bit asynchronous column-wise time-to-digital converter (TDC), enabling fast sensor readout whilst using minimal silicon area. Parallel output of 32 TDC interfaces are serialised to achieve fast data though-put. This system is implemented in a standard 0.18 μm standard CMOS technology, with a pixel size of 26 μm × 26 μm and a TDC of 26 μm × 180 μm. Simulation results demonstrate that chemical sampling of up to 5k frames per second can be achieved with a clock frequency of 160 MHz and a TDC resolution of 190 ps. The total power consumption of the overall system is 7.34 mW.

This paper presents an oscillator based potentiostat with switch-cap feedback for current sensing applications. In this work, a sigma-delta modulator is realized using current as input and charge as the feedback. The current input is integrated at the input capacitance and the voltage difference between the integrated value and reference input is converted to current via a transconductor. This current is then fed into a current controlled ring oscillator and the frequency output drives the switch-cap circuits to compensate the input current. Therefore, the current input can be directly readout as frequency deviation, or can be further converted to digital output via a frequency to digital converter. The proposed system is implemented in a typical 0.18μm CMOS technology, with total area of 80 × 250μm2. A differential structure was implemented to minimize the parasitic and kick back influence, with oscillator base frequency at 491MHz. A counter based frequency to digital converter with an additional CIC filter was implemented to convert the differential frequency signal to digital domains at 16MHz sampling frequency. Simulation results demonstrated that a dynamic range of 52dB was achieved with input range of ±2.5μA.

Next generation brain machine interfaces fundamentally need to improve the information transfer rate and chronic consistency when observing neural activity over a long period of time. Towards this aim, this paper presents a novel System-on-Chip (SoC) for a mm-scale wireless neural recording node that can be implanted in a distributed fashion. The proposed self-regulating architecture allows each implant to operate autonomously and adaptively load the electromagnetic field to extract a precise amount of power for full-system operation. This can allow for a large number of recording sites across multiple implants extending through cortical regions without increased control overhead in the external head-stage. By observing local field potentials (LFPs) only, chronic stability is improved and good coverage is achieved whilst reducing the spatial density of recording sites. The system features a ΔΣ based instrumentation circuit that digitises high fidelity signal features at the sensor interface thereby minimising analogue resource requirements while maintaining exceptional noise efficiency. This has been implemented in a 0.35 μm CMOS technology allowing for wafer-scale post-processing for integration of electrodes, RF coil, electronics and packaging within a 3D structure. The presented configuration will record LFPs from 8 electrodes with a 825 Hz bandwidth and an input referred noise figure of 1.77μVrms. The resulting electronics has a core area of 2.1 mm2and a power budget of 92 μW

This work presents a computationally efficient real-time adaptive clustering algorithm that recognizes and adapts to dynamic changes observed in neural recordings. The algorithm consists of an off-line training phase that determines initial cluster positions and an on-line operation phase that continuously tracks drifts in clusters and periodically verifies acute changes in cluster composition. Analysis of chronic recordings from non-human primates shows that adaptive clustering achieves an improvement of 14% in classification accuracy and demonstrates an ability to recognize acute changes with 78% accuracy, with significantly improved computational efficiency compared to the state-of-the-art. The presented algorithm is suitable for long-term chronic monitoring of neural activity in many applications of neuroscience research and control of neural prosthetics and assistive devices.

This paper presents a 64-bit on-chip identification system featuring low power consumption and randomness compensation for multi-node bio-implantable devices. A sense amplifier based bit-cell is proposed to realize the silicon physical unclonable function, providing a unique value whose probability has a uniform distribution and minimized influence from the temperature and supply variation. The entire system is designed and implemented in a typical 0.35 μm CMOS technology, including an array of 64 bit-cells, readout circuits, and digital controllers for data interfaces. Simulated results show that the proposed bit-cell design achieved a uniformity of 50.24% and a uniqueness of 50.03% for generated IDs. The system achieved an energy consumption of 6.0 pJ per bit with parallel outputs and 17.3 pJ per bit with serial outputs.

This paper presents a hardware realisation of a novel ECG baseline drift removal that preserves the ECG signal integrity. The microcontroller implementation detects the fiducial markers of the ECG signal and the baseline wander estimation is achieved through a weighted piecewise linear interpolation. This estimated drift is then removed to recover a “clean” ECG signal without significantly distorting the ST segment. Experimental results using real data from the MIT-BIH Arrhythmia Database (recording 100 and 101) with added baseline wander (BWM1) from the MIT-BIH Noise Stress Database show an average root mean square error of 34.3 μV (mean), 30.4 μV (median) and 18.4 μV (standard deviation) per heart beat.

This paper presents a multichannel, ultra-low-noise arbitrary signal generation platform for emulating a wide range of different biopotential signals (e.g. ECG, EEG, etc). This is intended for use in the test, measurement and demonstration of bioinstrumentation and medical devices that interface to electrode inputs. The system is organized in 3 key blocks for generating, processing and converting the digital data into a parallel high performance analogue output. These blocks consist of: (1) a Raspberry Pi 3 (RPi3) board; (2) a custom Field Programmable Gate Array (FPGA) board with low-power IGLOO® Nano device; and (3) analogue board including the Digital-to-Analogue Converters (DACs) and output circuits. By implementing the system this way, good isolation can be achieved between the different power and signal domains. This mixed-signal architecture takes in a high bitrate SDIO (Secure Digital Input Output) stream, recodes and packetizes this to drive two multichannel DACs, with parallel analogue outputs that are then attenuated and filtered. The system achieves 32-parallel output channels each sampled at 48kS/s, with a 10 kHz bandwidth, 110 dB dynamic range and μV-level output noise.

This paper presents a time-domain instrumentation circuit with exceptional noise efficiency directed at using nano metre CMOS for next generation neural interfaces. Current efforts to realize closed loop neuromodulation and high fidelity BMI prosthetics rely extensively on digital processing which is not well integrated with conventional analogue instrumentation. The proposed time-domain topology employs a differential ring oscillator that is put into feedback using a chopper stabilized low noise transconductor and capacitive feedback. This realization promises better digital integration by extensively using time encoded digital signals and seamlessly allows both clocked & unclocked ΔΣ behavior which is useful on-chip characterization and interfacing with synchronous systems. A 0.5 V instrumentation system is implemented using a 65 nm TSMC technology to realize a highly compact footprint that is 0.006 mm2 in size. Simulation results demonstrate an excess of 55 dB dynamic range with 3.5 μVrms input referred noise for the given 810 nW total system power budget corresponding to an NEF of 1.64.

The paper presents a novel topology of a continuous-time analogue-to-digital converter (CT-ADC) featuring ultra-low static power consumption, activity-dependent dynamic consumption, and a compact footprint. This is achieved by utilising a novel charge-packet based threshold generation method, that alleviates the requirement for a conventional feedback DAC. The circuit has a static power consumption of 3.75 μW, with dynamic energy of 1.39pJ/conversion level. This type of converter is thus particularly well-suited for biosignals that are generally sparse in nature. The circuit has been optimised for neural spike recording by capturing a 3 kHz bandwidth with 8-bit resolution. For a typical extracellular neural recording the average power consumption is in the order of ~4 μW. The circuit has been implemented in a commercially available 0.35 μm CMOS technology with core occupying a footprint of 0.12 mm2.

In this paper, we present a new method for neural spike sorting based on Continuous Time (CT) signal processing. A set of CT based features are proposed and extracted from CT sampled pulses, and a complete event-driven spike sorting algorithm that performs classification based on these features is developed. Compared to conventional methods for spike sorting, the hardware implementation of the proposed method does not require any synchronisation clock for logic circuits, and thus its power consumption depend solely on the spike activity. This has been implemented using a variable quantisation step CT analogue to digital converter (ADC) with custom digital logic that is driven by level crossing events. Simulation results using synthetic neural data shows a comparable accuracy compared to template matching (TM) and Principle Components Analysis (PCA) based discrete sampled classification.

This paper describes a new hardware-efficient method and implementation for neural spike sorting based on selection of a channel-specific near-optimal subset of features given a larger predefined set. For each channel, realtime classification is achieved using a simple decision matrix that considers the features that provide the highest separability determined through off-line training. A 32-channel system for online feature extraction and classification has been implemented in an ARM Cortex-M0+ processor. Measured results of the hardware platform consumes 268μW per channel during spike sorting (includes detection). The proposed method provides at least x10 reduction in computational requirements compared to literature, while achieving an average classification error of less than 10% across wide range of datasets and noise levels.

This paper presents a novel amplifier architecture intended for low power neural recording applications. By using continuous-time signal representation, the proposed topology predominantly leverages digital topologies taking advantage of efficient techniques used in time domain systems. This includes higher order feedback dynamics that allow direct analogue signal quantization and near ideal integrator structures for noise shaping. The system implemented in 0.18 μm standard CMOS demonstrates the capability for low noise instrumentation with a bandwidth of 6 kHz and highly linear full dynamic range. Simulation results indicate 1.145 μW budget from 0.5 V supply voltage with an input referred thermal noise of 7.7 μVrms.

This work presents a new data compression method that uses an energy operator to exploit the correlated energy in neural recording features in order to achieve adaptive sampling. This approach enhances conventional data converter topologies with the power saving of asynchronous systems while maintaining low complexity & high efficiency. The proposed scheme enables the transmission of 0.7kS/s, while preserving the features of the signal with an accuracy of 95%. It is also shown that the operation of the system is not susceptible to noise, even for signals with 1dB SNR. The whole system consumes 3.94μW with an estimated area of 0.093mm2.

This paper identifies and addresses key design considerations and trade-offs in the implementation of a CMOS high-resolution microheater array for Lab-on-Chip (LOC) applications. Specifically, this is investigated in the context of facilitating the in vitro thermal stimulation of single neurons. The paper analyses the electro-thermal response (by means of COMSOL simulations) and reliability issues (such as melting and electromigration) of different microheater designs. The analysis shows that a small-area heater is more efficient in terms of power, but it has more reliability problems essentially due to electromigration effects. For the proposed heater designs, the expected lifetime is a few days (in continuous operation) in the worst scenario, which is still generally acceptable for LOC applications.

This paper proposes a novel, octagonal shaped CMOS image sensor (CIS) array for use in tandem with colored LED illumination and a corresponding, innovative pixel scanning method. The octagonal shape of the pixel array allows the CIS to make near-optimal use of silicon real estate by matching the perimeter of the pixel array to the focal plane area of lenses used in Wireless Capsule Endoscopies (WCE). Providing illumination by sequencing different-colored LEDs allows the system to reuse the same pixels to capture different colors at different times, thus removing the need for manufacturing a Color Filter Array (CFA) and effectively trading temporal for spatial resolution. The system was designed with AMS 0.35µm 2P4M CMOS technology. The simulated system consumes 1.06 mW from a 2.5 V supply at 2.217 frames/sec operation.

This paper presents a novel method and circuit for feature-driven data acquisition in single neuron recording. By dynamically adjusting the phase of the sampling clock in a Successive Approximation Register (SAR) Analogue to Digital Converter (ADC), the samples can be maximally aligned to the spike extrema (peaks). This is achieved by using spike detection to switch from a `coarse' to `fine' sampling clock, and triggering a peak-search algorithm to determine the offset between the peak occurrence and the coarse clock. Subsequent samples are then aligned to the peak by shifting the coarse clock by the measured offset. This adaptive sampling scheme thus allows for improved temporal precision on features of interest (i.e. peaks) whilst maintaining a coarse effective sampling rate, also minimising power consumption. The proposed method reduces the output data bandwidth by approximately 70% in comparison to a fixed-sampling rate data converter that would achieve similar precision in peak alignment. The circuit implementation achieves 9-bit resolution with a 93 fJ/conversion-step energy efficiency in a standard 0.35 μm CMOS technology.

This work investigates the impact of the analogue front-end design (pre-amplifier, filter and converter) on spike sorting performance in neural interfaces. By examining key design parameters including the signal-to-noise ratio, bandwidth, filter type/order, data converter resolution and sampling rate, their sensitivity to spike sorting accuracy is assessed. This is applied to commonly used spike sorting methods such as template matching, 2ndderivative-features, and principle component analysis. The results reveal a near optimum set of parameters to increase performance given the hardware-constraints. Finally, the relative costs of these design parameters on resource efficiency (silicon area and power requirements) are quantified through reviewing the state-of-the-art.

This paper presents a novel front-end circuit for detecting action potentials in extracellular neural recordings. By implementing a real-time, adaptive algorithm to determine an effective threshold for robustly detecting a spike, the need for calibration and/or external monitoring is eliminated. The input signal is first pre-processed by utilising a non-linear energy operator (NEO) to effectively boost the signal-to-noise ratio (SNR) of the spike feature of interest. The spike detection threshold is then determined by tracking the peak NEO response and applying a non-linear gain to realise an adaptive response to different spike amplitudes and background noise levels. The proposed algorithm and its implementation is shown to achieve both accurate and robust spike detection, by minimising falsely detected spikes and/or missed spikes. The system has been implemented in a commercially available 0.18μm technology requiring a total power consumption of 1.5μW from a 1.8 V supply and occupying a compact footprint of only 0.03 mm2silicon area. The proposed circuit is thus ideally suited for highchannel count, calibration-free, neural interfaces.

The paper presents a novel ultra low power UWB transmitter system for near field communication in transcutaneous biotelemetries. The system utilizes an all-digital architecture based on minising the energy dissipated per bit transmitted by efficiently encoding a packet of pulses with multiple bits and utilizing oscillator referenced delays. This is achieved by introducing a novel bi-phasic 1.65pJ per pulse UWB pulse generator together with a 72 μW DCO that provide a transmission bandwidth of 77.5 Mb/s with an energy efficiency of 890 fJ per bit from a 1.2 V supply. The circuit core occupies a compact silicon footprint of 0.026 mm2in a 0.18μm CMOS technology.

This paper describes a novel integrated electrode interface for multi-polar stimulation of multi-electrode arrays. This interface allows for simultaneous stimulation using multiple electrodes configured as source or sink with different phase and amplitudes in order to perform field shaping inside the tissue. The system is designed in an high voltage 0.18 μm CMOS process with 8 channels. It features an output voltage swing of 16V and current up to 0.5mA for electrode impedences of up to 30kΩ which is suitable for cuff and cortical grid arrays. This electrode interface comprise a digital module which stores stimulation settings and operates the different electrode channels. Here we present the full system architecture and simulation results.

This paper presents an ultra-low-power 8-bit asynchronous current-mode (CM) successive approximation (SAR) analogue-to-digital converter (ADC) for single-neuron spike recording. The novel design exploits CM techniques to support operation at supply voltages down to 1.2V, consuming under 500nA at 16kSamples/s. The design features easy scalability, and allows for a tunable sampling frequency and dynamic range (DR). The circuit is designed in a commercially-available 0.18μm CMOS technology and occupies a chip area of 0.078mm2. The system requires a single, post-fabrication current calibration supported by on-chip circuitry to ensure robust operation through process and mismatch variations.

This paper presents a novel, fully-integrated circuit for achieving change-balanced voltage-mode neural stimulation based on a charge-metering technique. The proposed system uses two small on-chip capacitors, a counter, two comparators and a control-logic circuit to measure the charge delivered to the tissue. This has been designed to deliver a maximum charge stimulus of 10.24 nC within 100 μs. Simulated results show a charge delivery error of 0.4-4% and a maximum residual charge of -73 pC. Implemented in 0.18 μm CMOS, the total power consumption is 42 μW.

Charge-mode stimulation (ChgMS) is a relatively new method being explored in the field of electrical neural stimulation. One of the key challenges in such a system is to overcome charge sharing between the storage capacitor and the double layer capacitor in the Electrode-Electrolyte-Interface (EEI). In this work, this issue is overcome by using a second-generation negative current conveyor (CCII-) with a low current tracking error. The level of charge sharing in the circuit is expressed by a new figure of merit (charge delivery efficiency) introduced in this paper. The proposed system has a maximum power efficiency of 76.6% and a total power consumption of 270 μWper electrode for a target charge stimulus of 0.9 nC. Crucially, the system achieves a minimum charge delivery efficiency of 98.22%.

This paper presents a dynamic front-end towards achieving unsupervised single-neuron activity monitoring. By implementing at the front-end, an automatic gain control that is optimized for neural signal dynamics, subsequent processing can be achieved without the need for calibration. The system uses three amplification stages (low-noise first stage, variable-gain second stage and high-gain third stage), a tuneable high-pass filter, and a feedback loop to tune the variable gain. The circuit has been implemented in a commercially-available 0.18 μm CMOS technology with total power consumption between 1.79 and 1.95 μW. The front-end achieves a variable gain from 52 to 86.4 dB with 3 kHz bandwidth and a high-pass filter that is tuneable from 100-300 Hz. The input referred noise is 9.66 μV with a total harmonic distortion of under 1%.

This paper presents an energy-efficient neural stimulator capable of providing charge-balanced asymmetric pulses. Power consumption is reduced by implementing a fully-integrated DC-DC converter that uses a reconfigurable switched capacitor topology to provide 4 output voltages for Dynamic Voltage Scaling (DVS). DC conversion efficiencies of between 63% and 76% are achieved using integrated capacitances of under 1nF and the DVS approach offers power savings of up to 53.5% compared to the front end of a typical current controlled neural stimulator. A novel charge balancing method is used which has a low level of accuracy on a single pulse and a much higher accuracy over a series of pulses. The method used is robust to process and component variation and does not require any initial or ongoing calibration. Monte-Carlo simulations indicate that the charge imbalance can be less than 0.014% (at ±3σ) of charge delivered for a series of pulses. The circuit has been designed in a commercially-available 0.18µm HV CMOS technology and is estimated to require a die area of approximately 0.9mm2for a 16 channel implementation.

People rarely put in their papers the things that didn't work, the mistakes they made, and how they found out what went wrong. Such confessions can help others learn how to avoid similar mistakes. Twenty-six confessions were collected to form the bulk of this paper. Themes that arise are errors that result from not understanding the limitations of simulation tools in modeling physical reality, chip verification errors that result from lack of clear communication between designers, and projects that are considered in their own isolated environment of technical challenges rather than the broader context of their environment or application.

This paper presents a CMOS-based lab-on-chip platform for combined magnetic manipulation and opto-chemical sensing. Within each pixel, a Programmable Gate (PG) ISFET chemical sensor is combined with an active pixel sensor, and is encompassed within an inductive coil. The integrated pixel is tesselated to form an 8 × 8 array. Fabricated in a commercially available 0.35 μm CMOS technology, the system can be used for simultaneous optical imaging and pH sensing, and includes auto- calibration mechanisms for eliminating sensor non-idealities. A spatiotemporal magnetic field pattern generator has also been embedded for micro-scale magnetic manipulation. Controlled via a MATLAB based graphical user interface, the system achieves real time data acquisition at 6 fps, a pH sensitivity of 57 mV/pH and demonstrates magnetic manipulation of micro-beads.

In this paper, we present a novel, ultra-long-time-constant analogue integrator for a PID controller in Lab-on-Chip (LOC) applications. A time constant of up to 5 seconds is achievable using a capacitance of only 18pF by exploiting transconductance reduction techniques involving current splitting and gm-attenuated OTA. Additionally, this architecture provides the ability to digitally tune the time constant from 200ms to 5s with 4-bit programmability. The design achieves a temperature dependance of 1.2% over the range from 0°C to 100°C with micropower consumption.

This paper explores the concept of developing a bondpad-less fully-integrated inductive link for power/data transfer between a CMOS Integrated Circuit (IC) and a PCB. A key feature of the implemented system is that it requires no off-chip components. The proposed chip uses a standard 0.35 μm process and occupies an area of 2.5 mm × 2.5 mm and an on-chip inductor occupies an area of 1.5 mm × 1.5 mm. At 900 MHz, 9 mW was designed to be provided to the chip (up to 22.5 mW with a total efficiency of 5 %). Binary Phase Shift Keying (BPSK) and Load shift keying (LSK) are used for the the PCB-to-chip and chip-to-PCB link respectively for half-duplex communication. An Injection-Locked-Oscillator-based BPSK demodulator is implemented on-chip to save power. The maximum data rate for the PCB-to-chip link is lOMb/s. The estimated area of the circuitry is only 2 mm2which is 32 % of the total chip area.

This paper describes a mixed signal subsystem for the inductive transfer of power and data to a fully-implantable medical device. The design includes circuits for the inductive power recovery and energy storage (charging), in addition to data recovery and demodulation. The data link is used to upload (at a data rate of up to 180Kbps) calibration and configuration data to the implanted device and integrates both error detection and correction on the recovered bitstream. The system incorporates an implanted Li-Ion micro-battery with supporting charging hardware to provide an uninterrupted power supply for autonomous deployment. This is to provide continuous operation without the requirement for an externally worn unit and additionally ensures registry (i.e. patient calibration) settings are maintained. The circuit has been implemented in a commercially available 0.35µm CMOS technology without requiring high-voltage device options.

This paper describes an ASIC developed as part of a neural prosthesis to restore balance to individuals with a dysfunctional vestibular end-organ. The device interfaces with inertia sensors; sensing acceleration in five degrees of freedom (three radial and two linear axis), and then conditions, processes and converts the signals to provide the artificial stimulus to the vestibulocochlear nerve. The IC described herein has been realised as part of a board-level solution, also including the sensors, power source and DC blocking capacitors. It is envisaged that this can be later implemented in a system-in-package (SiP) form to provide a totally implantable solution. We describe the design and implementation of the integrated circuit in a standard 0.35 mum CMOS technology.

This paper presents a novel readout circuit for a pH sensitive programmable-gate ion-sensitive field effect transistor (PG-ISFET) to overcome bias issues due to threshold voltage variation and increase output-referred sensitivity. Compared to other commonly-used ISFET readouts, this circuit uses two extra programmable nodes which are driven by a feedback configuration. Using the device in a source follower configuration, one node is used to evaluate and cancel the offset of the intrinsic device while the other tracks and amplifies changes in pH. A sample and hold protocol has been developed to minimize the leakage effects and improve the pH sensing range. The system has been designed and fabricated in AMS 0.35 mum, to compensate for a threshold voltage variation of plusmn10.5 V and provide a pH sensitivity of 200 mV/pH.

This paper presents a novel hybrid CMOS/MEMS tilt sensor with a 5deg resolution over a 330deg range. The device uses a MEMS-based semicircular mass suspended from a rigid body, projecting a shadow onto the CMOS-based optical sensor surface. A one-dimensional photodiode array arranged as a uniformly segmented ring is then used to determine the tilt angle by detecting the position of the semicircular mass. The complete sensor occupies an area of under 2.5 m times 2.5 mm.

This papers presents a front-end circuit for interfacing to differential capacitive sensors, including certain micro- electromechanical systems (MEMS). The system combines a self- resetting, biphasic integrator with a difference timer, producing a word parallel output representing the differential capacitance. The measurable capacitance range is tunable by means of an input current bias and system clock frequency. For an input bias of lOnA and system clock of 128 KHz, the measurable capacitance range is +/-5 pF (to 8 bit resolution) consuming below 26 muW total system power.

This paper describes a novel partial-current-steering stimulation drive for implantable neural prosthetics. The drive hardware momentarily delivers a charge-balanced asymmetric stimulus to a dummy load before steering towards the stimulation electrodes. In this fashion, power is conserved whilst still gaining from the benefits of current steering. The circuit has been designed to be digitally programmable as part of an implantable vestibular prosthesis. The hardware has been implemented in AMS 0.35 mum 2P4M CMOS technology.

This demonstrator presents an ultra low power mixed-signal implementation of a cochlear prosthesis system. A laptop PC provides an audio stimulus to the cochlear chip. A microcontroller on the demonstrator board monitors the output channels of the chip and returns these to the PC to be displayed as a spectrogram. The audiological settings of the implant chip are controlled via a GUI running on the PC.

In this work we present an adaptable foveating vision chip. This chip has no physical foveation; all its pixels are in the same uniform pattern. However with a given input signal it is possible to define areas of the chip which act as a fovea, returning high spatial resolution. The surrounding peripheral vision acts to return lower spatial resolution but much higher temporal resolution. Our chip is therefore able to achieve full spatial resolution via scanning of the fovea across the visual field. This operation is analogous to the functioning of the human eye. In the human eye however, the limitations of biology enforce a fixed fovea, while the optomechanics are highly efficient. In our structure, we acknowledge the limitations of physical optomechanics but use the advantages of silicon processing to achieve dynamic foveation. This paper discusses the algorithm, its implementation and simulated results describing its responses and power consumption

A hybrid vision chip is presented for real-time object-based processing for tasks such as positioning and sizing of enclosed objects. This system presents the first artificial silicon retina capable of position and size determination of multiple objects in true parallel fashion. Based on a novel distributed algorithm, this approach uses the input image to enclose a feedback loop to realise a data-driven pulsating action. The fabricated device is shown to achieve a computation-efficiency of at least 725 million instructions per second per milliwatt and capable of processing up to 2000 frames per second