A transformer-based end-to-end detection method lightweight sonar detection transformer (LS-DETR) is proposed, which is specifically tailored for enhancing detection accuracy in forward-looking sonar images while significantly reducing the computational load. Despite the challenges posed by the complexity of underwater environments that have led to suboptimal detection performance and the lack of lightweight optimization for underwater devices, LS-DETR addresses these issues effectively. In LS-DETR, the backbone employs a newly proposed lightweight gated attention block (LGABlock), which reduces computational redundancy through low-complexity convolutions and gated attention. A lightweight hybrid encoder (LHE) is designed to facilitate scale-internal feature interaction and optimize the feature fusion approach. Furthermore, WCIoU-aware query selection is proposed and integrated with NWDLoss in the decoder, enabling the scores to integrate classification and positional information while focusing on the small targets. Results demonstrate that on the multi-beam forward-looking sonar dataset UATD, LS-DETR achieved a 2.8% increase in accuracy and a 31.5% reduction in parameter count, proving the effectiveness and superiority.

Physics theory integrated machine learning models enhance the interpretability and performance of artificial intelligence (AI) techniques to real-world industrial applications, such as the fault detection and diagnosis (FDD) of air handling units (AHU). Traditional machine learning-based automated FDD model demonstrates a high classification accuracy with sufficient training data samples, however, suffers from physical interpretation of the machine learning models. In this article, a physical model integrated Wasserstain generative adversarial network (WGAN) model is presented for AHU FDD with a scenario of insufficient training data samples. The proposed solution tackles the real-world problem of AHU FDD and enhances the model interpretability significantly. A transformer-WGAN model is designed to further improve the proposed FDD framework. Experimental results show that the proposed method outperforms existing AHU FDD methods with imbalanced real-world training data samples.

We propose a novel architecture of memory controller, called HMC (Heterogeneous Multi-Channel), as an improvement to the previous homogeneous multi-channel memory controller. HMC groups physical DRAM devices into logical sub-ranks with different data bus width, and controls them simultaneously. Employing new proposed memory access algorithm, HMC manages the number of devices involved in a single memory access flexibly, and achieves the best performance/power efficiency. Using four-core multiprogramming workloads, our experimental results show that HMC improves system performance by 27.6% with 24.2% reduction in DRAM power consumption on average.

This paper presents a new memory access scheduler, called FSCM (Fair Service Curve Memory access scheduler), which targets for the objective that provides the highest system throughput. The main idea of reordering memory access requests based on the service curve is borrowed from the literature of packet-switched networks. Different threads have different QoS (Quality-of-Service) requirements, and FSCM assigns each thread a service curve. The service curve gives great adaptability to FSCM in allocating its bandwidth. We evaluate FSCM using multi-threaded applications, and compare it to three previously proposed memory access schedulers. On a four-core CMP running combinations of workloads with a wide range of memory bandwidth and latency requirements, FSCM improves system performance by 16.7% on average, and provides the best fairness to all of the threads.