Experiential learning opportunities (study abroad, service learning, and research experiences) support and enable the continuing evolution of undergraduate engineering programming from a focus on the ‘curriculum’ to the ‘experience.’ Orchestrating large-scale research programs for undergraduates presents significant challenges related to programming, the research itself, engineering professional formation, and assessment of all three. This paper reports on two continuous years' implementation of a large-scale undergraduate summer research program focused on technical research in energetic materials supported by the US Department of Defense via the Army Research Laboratory (ARL). The design and execution of the program were non-trivial and contained challenges and affordances. Evidence-based practice was used to justify program improvements. The paper describes four important design considerations: (i) the appropriate balance between technical research experience and programmatic activities focused on engineering professional formation, (ii) the creation of a “human talent pathway” from undergraduate students to potential graduate students to potential energetic materials scientists and engineers employed by the ARL, (iii) the development of interest in relevant careers and (iv) the promotion of graduate school. Using evidence-based practice, thematic analysis, and continuous improvement frameworks, we assessed each element of the overall program through quantitative and qualitative surveys of student researchers and their mentors across two implementations. Our measurements indicate tension between the technical and professional goals of the program. The second iteration of the program shifted the balance towards technical research. It decreased the role of formal professional development activities while re-committing to the workforce elements of the experience. We conclude that streamlined programs with low-frequency, high-impact events complementing the research allow students to retain the most meaning and knowledge. We provide examples of lessons learned through our continuous improvement process, including the importance of student and mentor feedback and flexibility in program content and delivery. Finally, we present recommendations for the pedagogical design of future undergraduate research programs, including accommodating cohorts with diverse educational backgrounds.

In this paper, we propose a novel methodology for machine learning-based hotspot detection that uses lithography information to build support vector machine (SVM) during its learning process. Unlike previous studies that use only geometric information or require a post-optical proximity correction (OPC) mask, this proposed method utilizes detailed optical information but bypasses post-OPC mask by sampling latent image intensity and uses those points to train an SVM model. The results suggest high accuracy and low false alarm, and faster runtime compared with methods that require a post-OPC mask.

Directed self assembly (DSA) is a very promising candidate for the sub-7 nm technology nodes. To print such small dimensions, multiple patterning (MP) is likely to be used to print the guiding templates for DSA. Therefore, algorithms are required to perform the DSA grouping at the same time as the mask assignment. In this paper, we present an optimal integer linear program (ILP) to solve this problem for two schemes of hybrid DSA-MP process. Scalable heuristic algorithms are also proposed to solve the same problem. In comparison to the ILP, the proposed heuristics are 4×-213× faster, and result in an increase of total number of violations by 4%-29%.

Integrating Directed Self Assembly (DSA) and Multiple Patterning (MP) is an attractive option for printing contact and via layers for sub-7nm process nodes. In the DSA-MP hybrid process, an optimized decomposition algorithm is required to perform the MP mask assignment while considering the DSA advantages and limitations. In this paper, we present an optimal Integer Linear Programming (ILP) formulation for the simultaneous DSA grouping and MP decomposition problem for contacts and vias. Then we propose a heuristic and develop an efficient algorithm for solving the same problem. In comparison to the optimal ILP results, the proposed algorithm is 197x faster and results in 16.3% more violations. The proposed algorithm produces 56% fewer violations than the sequential approaches which perform DSA grouping followed by MP decomposition and vice versa.

Modern CMOS technologies employ process-induced stress to improve carrier mobility and increase drive current. This stress has been shown to be strongly layout dependent; however there is a lack of physical models relating potential performance variation to critical layout parameters. This paper presents compact closed-form models that capture the layout dependence of mechanical stress induced in the device channel while considering all relevant sources of stress (STI, tensile/compressive nitride liners, and embedded SiGe). The models are calibrated using ring oscillator frequency data obtained from an experimental test chip to verify their accuracy. Results indicate that the models accurately capture the layout dependence of stress and carrier mobility for a variety of layout permutations and the root mean square error in the predicted ring oscillator frequency is less than 1% for the different layout experiments. These models can help drive layout optimization and timing/power analysis without the use of technology computer-aided design (TCAD) tools, which are slow and very limited in capacity.

SSTA has received a considerable amount of attention in recent years. However, it is a general rule that any approach can only be as accurate as the underlying models. Thus, variation models are an important research topic, in addition to the development of statistical timing tools. These models attempt to predict fluctuations in parameters like doping concentration, critical dimension (CD), and ILD thickness, as well as their spatial correlations. Modeling CD variation is a difficult problem because it contains a systematic component that is context dependent as well as a probabilistic component that is caused by exposure and defocus variation. Since these variations are dependent on topology, modern-day designs can potentially contain thousands of unique CD distributions. To capture all of the individual CD distributions within statistical timing, a transistor-specific model is required. However, statistical CD models used in industry today do not distinguish between transistors contained within different standard cell types (at the same location in a die), nor do they distinguish between transistors contained within the same standard cell. In this work we verify that the current methodology is error-prone using a 90 nm industrial library and lithography recipe (with industrial OPC) and propose a new SSTA delay model that on average reduces error of standard deviation from 11.8% to 4.1% when the total variation (sigma/mu) is 4.9% - a 2.9X reduction. Our model is compatible with existing SSTA techniques and can easily incorporate other sources of variation such as random dopant fluctuation and line-edge roughness.