A one-dimensional gate assignment algorithm based on hierarchical contraction of nets is proposed. In this algorithm, a special feature of multiterminal nets plays an important role, namely that if the gates can be arranged such that the nets with fewer terminals are shorter, the chip area will be much reduced. The algorithm consists of two phases, hierarchical contraction of nets and partial gate assignment. In the first phase, the original problem is partitioned to multiple levels with the basis on contraction of multiterminal nets, and in the next phase, the gates at each level are placed close to one another. Experimental results on logic circuits are shown which are superior to those obtained by the method presented by T. Fujii, et al. (ibid., vol.CAD-6, no.3, p.159-64, March 1987).>

This paper deals with the optimum assignment of job modules onto array processors. In array processors it is important to assign job modules onto processors such that the modules that communicate with each other are assigned to adjacent processors, because communication overhead increases as communications occur between processors that are remotely connected. We propose an efficient algorithm to solve this assignment problem for a specific array of processors. The algorithm reduces the quadratic problem to a solvable linear problem that produces a good, but not necessarily optimal solution. This is followed by a phase of iterations in which the solution is improved by small perturbation of the assignment.

This paper introduces a graph space that shows concisely the relative weights among combinations of vertices of a given hypergraph. (A hypergraph is a graph in which one edge may connect two or more vertices.) The hypergraph is represented by a collection of points in graph space such that the distance between vertices in graph space reflects the weights of the edges between vertices of the original hypergraph. Vertices of the hypergraph that are connected by edges with large weights are mapped to nearby points in graph space. Thus, graph space reveals properties of the connectivity of vertices in the hypergraph. A natural application of graph space is the placement of modules in computer systems since strongly coupled modules are transformed into nearby points in graph space. The graph of the airlines network in the United States is taken as an example of a hypergraph, and the paper illustrates the corresponding graph space.

In this paper we propose a new method for correcting garbled words based on Levenshtein distance and weighted Levenshtein distance. We can correct not only substitution errors, but also insertion errors and deletion errors by this method. According to the results of simulation on nearly 1000 high occurrence English words, higher error correcting rates can be achieved by this method than any other method tried to date. Hardware realization of the method is possible, though it is rather complicated.

Block codes are constructed that are capable of simultaneously correctingeor fewer synchronization errors intconsecutive words, for anyt \geq 2e + 1, andsor fewer substitution errors in eachoft - 1or fewer of these words under the condition that there exists at least one ungarbled word among thetconsecutive words. Also, some new extensions of theA_{n}^{c}codes of Calabi and Hartnett are presented under the condition that synchronization and substitution errors do not coexist in thetconsecutive words.