With the recent spread of Internet of Things (IoT) devices, security issues for hardware devices have been increasing. There are several methods proposed for analyzing power consumption of hardware devices to detect anomalous behavior of such devices. SARIMA is used to analyze steady-state time-series data, that is considered quite effective for detecting anomalous behavior of IoT devises. In this paper, we propose a method for detecting anomalous behavior of IoT devices based on a reference waveform using SARIMA. The proposed method extracts application power waveforms from measured power waveforms using the autoencoder. Then, a reference waveform is generated from the obtained application power waveforms using SARIMA, and compared to detect anomalous behaviors. We applied the proposed method to an IoT device implemented using the Raspberry Pi4, and succeeded in detecting anomalous behaviors by generating a highly accurate reference waveform using SARIMA, while the state-of-the-art recent method cannot detect them.

The heterogeneous users travel planning problem (HUTPP) is an optimization problem and it seeks to identify the routes maximizing shared experiences while managing the conflicts over points of interest (POIs) between different users. Conventional methods and solvers using von Neumann computers offer good approximate solutions to optimization problems, but the solution quality may not be guaranteed with limited time costs. On the other hand, Ising machines or quantum annealing machines are non-von Neumann computers that are effective in solving complicated optimization problems. In this paper, we propose an Ising-based method to effectively solve the HUTPP and evaluate the proposed method on a real-world area, Sapporo, Japan. According to the comparison with a conventional method and a conventional solver, the empirical results suggest that the proposed methods outperform the conventional method and solver regarding solution quality, especially with a > 14 % improvement in POI sharing degree.

In the fourth industrial revolution, securing the protection of supply chains has become an ever-growing concern. One such cyber threat is a hardware Trojan (HT), a malicious modification to an IC. HTs are often identified during the hardware manufacturing process but should be removed earlier in the design process. Machine learning-based HT detection in gate-level netlists is an efficient approach to identifying HTs at the early stage. However, feature-based modeling has limitations in terms of discovering an appropriate set of HT features. We thus proposeNHTD-GLin this paper, a novel node-wise HT detection method based on graph learning (GL). Given the formal analysis of the HT features obtained from domain knowledge,NHTD-GLbridges the gap between graph representation learning and feature-based HT detection. The experimental results demonstrate thatNHTD-GLachieves 0.998 detection accuracy and 0.921 F1-score and outperforms state-of-the-art node-wise HT detection methods.NHTD-GLextracts HT features without heuristic feature engineering.

With the recent spread of Internet of Things (IoT) devices, the security issues for hardware devices have increased. When an IoT device runs an application program, the power consumption of the running application is combined with the power consumption of the device hardware itself, resulting in a complex power waveform. To detect anomalous application behaviors using the power waveforms, it is necessary to subtract the steady-state power waveform due to the device hardware from the measured power waveforms and extract only the application power waveform. In this paper, we propose a method for detecting anomalous IoT behaviors using generated power waveforms by introducing hyper-parameter tuning. The proposed method detects anomalous behaviors by generating a highly accurate steady-state power waveform and an application power waveform by adjusting the waveform period through hyper-parameter tuning, even if the measured power waveform includes large noises. Experimental evaluation demonstrates that we successfully detect anomalous behaviors from an AES encryption circuit containing a hardware Trojan on an FPGA device, while the existing state-of-the-art method cannot.

Graph neural networks (GNNs) have been actively employed in hardware security and have demonstrated remarkable performance. In particular, GNN models for hardware Trojan (HT) detection significantly outperform existing machine learning-based detection methods. However, GNNs have a potential vulnerability to membership inference attack (MIA), which aims to determine whether a given sample is used in the training dataset. In this paper, we investigate the threat of MIAs for GNN-based HT detection models. First, the MIA scheme for GNN-based HT detection models is established based on the basic MIA settings. The experimental results demonstrate that MIA for GNN-based HT detection can leak information about the HTs included in the training dataset with a 0.945 attack AUC score in the worst-case scenario. Based on this observation, we propose a defense method against MIA utilizing a domain generalization technique. The proposed defense method successfully mitigated the vulnerability of MIA and degraded the attack AUC score to 0.536 for the netlist level while maintaining the original HT detection performance.

Hardware Trojans (HTs) have become a serious problem, and extermination of them is strongly required for enhancing the security and safety of integrated circuits. An effective solution is to identify HTs at the gate level via machine learning techniques. However, machine learning has specific vulnerabilities, such asadversarial examples. In reality, it has been reported that adversarial modified HTs greatly degrade the performance of a machine learning-based HT detection method. Therefore, we propose a robust HT detection method using adversarial training (R-HTDetector). We formally describe the robustness of R-HTDetector in modifying HTs. Our work gives the world-first adversarial training for HT detection with theoretical backgrounds. We show through experiments with Trust-HUB benchmarks that R-HTDetector overcomes adversarial examples while maintaining its original accuracy.

A merge process is proposed to engineer a multi-spin flip in an Ising machine. The merge process deforms the Hamiltonian (energy function) of the Ising model. We prove a theorem for the merge process and show that a single-spin flip in the deformed Hamiltonian is equivalent to a multi-spin flip in the original Hamiltonian. A merge process induces a transition within the subspace of feasible solutions. We propose a hybrid simulated annealing (SA) algorithm with the merge process. The hybrid algorithm outperforms the conventional SA algorithm, genetic algorithm, and tabu search in the binary quadratic knapsack problems (QKP) and the quadratic assignment problems (QAP). Finally, the hybrid merge process is used in a real Ising machine. The performance is improved in QKP and QAP instances. The merge process is generally applicable to existing Ising machine hardware because the deformed Hamiltonian keeps the format of the Ising model.

We propose a spin-variable reduction method for Ising machines to handle linear equality constraints in a combinatorial optimization problem. Ising machines including quantum-annealing machines can effectively solve combinatorial optimization problems. They are designed to find the lowest-energy solution of a quadratic unconstrained binary optimization (QUBO), which is mapped from the combinatorial optimization problem. The proposed method reduces the number of binary variables to formulate the QUBO compared to the conventional penalty method. We demonstrate a sufficient condition to obtain the optimum of the combinatorial optimization problem in the spin-variable reduction method and its general applicability. We apply it to typical combinatorial optimization problems, such as the graph κ-partitioning problem and the quadratic assignment problem. Experiments using simulated-annealing and quantum-annealing based Ising machines demonstrate that the spin-variable reduction method outperforms the penalty method. The proposed method extends the application of Ising machines to larger-size combinatorial optimization problems with linear equality constraints.

In this study, we present an autonomous driving sys-tem that utilizes a binarized autoencoder implemented on a Field Programmable Gate Array (FPGA). The binarized autoencoder compresses the image into optimal features in this system. The recurrent neural network then determines the following control based on the feature values extracted from the autoencoder and the rotation speed of the motor. We reduced the model size by binarizing the autoencoder because of the limited on-chip memory of the FPGA. We implemented the system on an Ultra96-V2, a board with a programmable logic and processing system. The robot employing our implemented system exhibits robust control by recognizing the entire road marking and road edge line as a feature and drives autonomously along the specified route.

In recent years, with the wide spread of the Internet of Things (IoT) devices, security issues for hardware devices have been increasing, where detecting their anomalous behaviors becomes quite important. One of the effective methods for detecting anomalous behaviors of IoT devices is to utilize operation duration time and consumed energy extracted from their power waveforms. However, the existing methods do not consider the shape of time-series data and cannot distinguish between power waveforms with similar duration time and consumed energy but different shapes. In this paper, we propose a method for detecting anomalous behaviors based on the shape of time-series data by incorporating a shape-based distance (SBD) measure. The proposed method firstly obtains the entire power waveform of the target IoT device and extract several application power waveforms. After that, we give the invariances to them and we can effectively obtain the SBD between every two application power waveforms. Based on the SBD values, the local outlier factor (LOF) method can finally distinguish between normal application behaviors and anomalous application behaviors. Experimental results demonstrate that the proposed method successfully detects the anomalous application behaviors, while the existing method fails to detect them.

Recently, with the increase in outsourcing of IC design and manufacturing, the possibility of inserting hardware Trojans, which are circuits with malicious functions, has been pointed out. To prevent this threat, a method to identify hardware Trojans using neural networks has been proposed. On the other hand, adversarial attacks have emerged that modify circuit design information to reduce the accuracy of hardware-Trojan classification by neural networks. Since the features designed by existing methods do not take the attacks into account, it is necessary to consider a new method for countermeasures. In this paper, out of 76 features that are strongly related to hardware-Trojan features, we investigate them from the viewpoint of the robustness against the adversarial attacks on circuit design information and newly propose 24 hardware-Trojan features. We compare the classifiers using the proposed 24 features with the classifiers using 11, 36, 51, and 76 existing features, respectively and confirm that the proposed ones are more robust in identifying hardware Trojans in circuits subjected to the adversarial attacks.

Ising machines are expected to solve combinatorial optimization problems efficiently by representing them as Ising models or equivalent quadratic unconstrained binary optimization (QUBO) models . However, upper bound exists on the computable problem size due to the hardware limitations of Ising machines. This paper propose a new hybrid annealing method based on partial QUBO extraction, called subQUBO model extraction, with multiple solution instances. For a given QUBO model, the proposed method obtains$N_I$quasi-optimal solutions (quasi-ground-state solutions) in some way using a classical computer. The solutions giving these quasi-optimal solutions are calledsolution instances. We extract a size-limited subQUBO model as follows based on a strong theoretical background: we randomly select$N_S$$(N_S

Annealing machines have been developed as non-von Neumann computers aimed at solving combinatorial optimization problems efficiently. To use annealing machines for solving combinatorial optimization problems, we have to represent the objective function and constraints by an Ising model, which is a theoretical model in statistical physics. Further, it is necessary to transform the Ising model according to the hardware limitations. In the transformation, the process of effectively reducing the bit-widths of coefficients in the Ising model has hardly been studied so far. Thus, when we consider the Ising model with a large bit-width, a naive method, which means right bit-shift, has to be applied. Since it is expected that obtaining highly accurate solutions is difficult by the naive method, it is necessary to construct a method for efficiently reducing the bit-width. This article proposes methods for reducing the bit-widths of interaction and external magnetic field coefficients in the Ising model and proves that the reduction gives theoretically the same ground state of the original Ising model. The experimental evaluations also demonstrate the effectiveness of our proposed methods.

This paper presents an autonomous driving system utilizing FPGA-based image processing. We develop a robot that our system is implemented on Ultra96-V2, a board with programmable logic and processing system. We use ROS, a middleware framework for developing robots, to manage the system such as controlling hardware devices, localization and determination of the direction to go. We implement a neural network to detect road markings on the road on a programmable logic on the board. The robot with our system implemented drives autonomously along the specified route on a miniature road, recognizing edge line and road markings.

Due to the rapid growth in the information and telecommunications industries, an untrusted vendor might compromise the complicated supply chain by inserting hardware Trojans (HTs). Although hardware Trojan detection methods at gate-level netlists employing machine learning have been developed, the training dataset is insufficient. In this paper, we propose a data augmentation method for machine-learning-based hardware Trojan detection. Our proposed method replaces a gate in a hardware Trojan circuit with logically equivalent gates. The experimental results demonstrate that our proposed method successfully enhances the classification performance with all the classifiers in terms of the true positive rates (TPRs).

Recently, with the spread of Internet of Things (IoT) devices, embedded hardware devices have been used in a variety of everyday electrical items. Due to the increased demand for embedded hardware devices, some of the IC design and manufacturing steps have been outsourced to third-party vendors. Since malicious third-party vendors may insert malicious circuits, called hardware Trojans, into their products, developing an effective hardware Trojan detection method is strongly required. In this paper, we propose 25 hardware-Trojan features based on the structure of trigger circuits for machine-learning-based hardware Trojan detection. Combining the proposed features into 11 existing hardware-Trojan features, we totally utilize 36 hardware-Trojan features for classification. Then we classify the nets in an unknown netlist into a set of normal nets and Trojan nets based on the random-forest classifier. The experimental results demonstrate that the average true positive rate (TPR) becomes 63.6% and the average true negative rate (TNR) becomes 100.0%. They improve the average TPR by 14.7 points while keeping the average TNR compared to existing state-of-the-art methods. In particular, the proposed method successfully finds out Trojan nets in several benchmark circuits, which are not found by the existing method.

Hardware security issues have emerged in recent years as Internet of Things (IoT) devices have rapidly spread. Power analysis is one of the methods to detect anomalous operations, but it is hard to apply it to IoT devices where an operating system and various software programs are running and hence its power waveforms become more complex. In this paper, we propose an anomalous behavior detection method utilizing application-specific power behaviors extracted by steady-state power waveform, which is generated by LSTM (long short-term memory). The proposed method is based on extracting application-specific power behaviors by predicting steady-state power waveforms. At that time, by using LSTM, we can effectively predict steady-state power waveforms, even if they include one or more cycled waveforms and/or they are composed of many complex waveforms. In the experiment, we implement three normal application programs and one anomalous application program on a single board computer and apply the proposed method to it. The experimental results demonstrate that the proposed method successfully detects the anomalous power behavior of an anomalous application program, while the existing method cannot.

A heuristic algorithm is one of the approaches to solve an NP-hard problem. In order to enhance the capability of the system, heterogeneous computing is often adapted. In this paper, we propose an FPGA-based heterogeneous solver for three-dimensional routing. The proposed system is implemented into multiple FPGA boards and a single-board computer. The experimental results demonstrate that the proposed system outperforms a single FPGA system.

Ising machines are a new type of non-Neumann computer that specializes in solving combinatorial optimization problems efficiently. The input form of Ising machines is the energy function of the Ising model or quadratic unconstrained binary optimization form, and Ising machines operate to search for a condition to minimize the energy function. We describe the theory of Ising machines and the present status of the Ising machines, software for Ising machines, and applications using Ising machines.

Recently, with the spread of Internet of Things (IoT) devices, embedded hardware devices have been used in a variety of everyday electrical items. Due to the increased demand for embedded hardware devices, some of the IC design and manufacturing steps have been outsourced to third-party vendors. Since malicious third-party vendors may insert hardware Trojans into their products, developing an effective hardware Trojan detection method is strongly required. In this paper, we evaluate hardware Trojan detection methods using neural networks and random forests at gate-level intellectual property (IP) cores that contain more than 10,000 nets. First, we extract 11 features for each net in a given netlist, and learn them with neural networks and random forests. Then, we classify the nets in an unknown netlist into a set of normal nets and Trojan nets based on the learned classifiers. The experimental results demonstrate that the average true positive rate becomes 84.6% and the average true negative rate becomes 95.1%, which is sufficiently high accuracy compared to existing evaluations.

With the widespread use of Internet of Things (IoT) devices in recent years, we utilize a variety of hardware devices in our daily life. On the other hand, hardware security issues are emerging. Power analysis is one of the methods to detect anomalous operations, but it is hard to apply it to IoT devices where an operating system and various software programs are running. In this paper, we propose an anomalous behavior detection method for an IoT device by extracting application-specific power behaviors. First, we measure a power consumption of an IoT device, and obtain the power waveform. Next, we extract an application-specific power waveform by eliminating a steady factor from the obtained power waveform. Finally, we extract feature values from the application-specific power waveform and detect an anomalous behavior by utilizing the local outlier factor (LOF) method. The experimental results using a single board computer demonstrate that the proposed method successfully detects the anomalous power behavior of an anomalous application program.

Since hardware/software vendors produce their IoT products easily and inexpensively, they often outsource their designs to third-party vendors where malicious third-party vendors can have a chance to insert software Trojans as well as “hardware Trojans” into their IoT devices. How to tackle the issue becomes a serious concern these days. In this paper, we propose an anomaly behavior detection method utilizing accurate power analysis for low-cost micro-controllers. Our method accurately measures power consumption of the target device, and then classifies its waveform into the sleep-mode part, in which a micro-controller saves power, and into the active-mode part, in which a micro-controller works in a normal operation. After that, we obtain the duration time and consumed power from each active-mode period as feature values. Finally, we detect abnormal behavior based on the obtained feature values utilizing an outlier detection method. In our experiments, we empirically evaluate the proposed method utilizing two types of micro-controllers, and the experimental results demonstrate that our proposed method successfully detects abnormal behaviors.

In electric circuits, errors are ineluctable. When upper bits of binary signals flip due to noise, the value will increase or decrease drastically. On the other hand, if stochastic numbers are used, the change on their values are the same since all the bits have the same weight. Therefore, stochastic computing, a computation method based on stochastic numbers, is attracting interest. Stochastic computing does have error tolerance, but cannot restore the bit stream if the bits are erroneous. Here, this paper focuses on evaluating the error-free value from the bit error rate and the erroneous value. In this paper, we propose a method to correct errors of stochastic numbers by measuring the bit error rate and filtering the values properly. From experimental evaluations, in environment with errors of more than 21%, this proposal will give a better peak-signal-to-noise ratio compared with a conventional error correction coding.

Faithfully truncated adders are used for low cost FIR implementations in this paper, which improves state-of-the-art CSD-based FIR filter designs for further area and power reduction while meeting the accuracy requirement. As a solution to the accuracy loss caused by truncated adders, this paper performed a static error analysis of truncated adders. Furthermore, based upon our mathematical analysis, we show that, with a given accuracy constraint, an optimal truncated adder configuration can be effortlessly determined for area-power efficient FIR designs. Evaluation results on various FIR designs showed that 16.8%~35.4% reduction in area and 11.8%~27.9% in power saving can be achieved with the proposed optimal truncated adder designs within an average error of 1 ulp.

Online media communities have globally spanned and have increasingly accelerated the development of intelligent travel recommendation systems in both academic and industrial fields. However, there is a bottleneck that differences in users' seasonal travel distributions (when to visit) in various language groups are ignored. This paper proposes a seasonal activity prediction algorithm based on user comments over the period of 2012 to 2017 in different language groups. We take the advantage of online user comments which provide visiting time for each landmark and detailed activity description. With the accumulation of 417,787 user comments on TripAdvisor for 300 landmarks in three big cities, we analyze the language-specific differences in travel distributions. After that, prediction of future travel distribution for each language group is generated. Then potential peak and off seasons of each landmark are distinguished and representative seasonal activities are extracted through comment contents for peak and off seasons, respectively. Experimental results in the three cities show that the proposed algorithm is more accurate in terms of peak season detection and seasonal activity prediction than previous studies.

Microcontrollers are widely used in electric devices such as smart phones, televisions, and other smart IoT (Internet-of-Things) devices. Because of the increase of these smart IoT devices, the security of hardware devices becomes a serious concern. In this paper, we propose a method which detects the existence of malfunctions implemented in microcontrollers utilizing power analysis. Our method firstly measures power consumption of the target device and classifies its waveform into the sleep-mode part, in which a microcontroller saves power, and the active-mode part, in which a microcontroller works in a normal operation. After that, we focus on the active-mode part and extract several features from the waveform, which effectively distinguish between normal operations and malfunctions. Finally, we classify the features and identify whether malfunctions exist or not. Our experimental results demonstrate that our proposed method successfully detects the existence of malfunctions in our benchmark.

Due to the continuous demand of small-sized circuits in the fields of image processing and artificial intelligence, stochastic computing has attracted much attention. In stochastic computing, stochastic numbers composed of randomly generated bit streams are used for computation. When inputting two or more identical values to a stochastic circuit, their arithmetic operation results can be inaccurate. In this paper, a stochastic number duplicator called RRR (Register based Re-arrangement circuit using a Random bit stream) duplicator is introduced and is evaluated by applying to composite arithmetic circuits including re-convergence paths. The stochastic numbers duplicated by RRR duplicator have the equivalent values to its input stochastic numbers but have independent bit streams, effectively utilizing bit re-arrangement based on randomized bit streams. It is applied to composite arithmetic circuits and its accuracy and area/delay requirements are evaluated. The results demonstrate that RRR duplicator obtains more accurate results in a circuit with re-convergence paths, reducing the mean square errors by 64%- 94% compared to a conventional stochastic number duplicator.

Recently, high-functioning hardware devices such as smart TVs and smart phones have been widely used in our daily lives. To keep up with the rapid advance of these high technologies, reconfigurable hardware devices such as FP-GAs (Field Programmable Gate Arrays) have been used in final products. Under the circumstances, the risks that mal-functions may be inserted into hardware devices have arisen. The malfunctions inserted into hardware devices are known as hardware Trojans. How to detect them becomes serious concern in hardware production. In this paper, we design a Trojan-infected cryptographic circuit as well as a Trojan-invalidating circuit, and implement them on an FPGA board. To begin with, we design an AES cryptographic circuit. Secondly, we insert a hardware Trojan into the AES cryptographic circuit. Finally, we design a Trojan-invalidating circuit and insert it into a suspicious Trojan net in the Trojan-infected cryptographic circuit. After that, we implement the circuits into an FPGA board. The experimental results demonstrate that the Trojan-invalidating circuit adequately deactivate the suspicious Trojan net in the Trojan-infected cryptographic circuit.

Recently, due to the increase of outsourcing in IC design and manufacturing, it has been reported that malicious third-party IC vendors often insert hardware Trojans into their products. Especially in IC design step, it is strongly required to detect hardware Trojans because malicious third-party vendors can easily insert hardware Trojans in their products. In this paper, we propose a machine-learning-based hardware-Trojan detection method for gate-level netlists using multi-layer neural networks. First, we extract 11 Trojan-net feature values for each net in a netlist. After that, we classify the nets in an unknown netlist into a set of Trojan nets and that of normal nets using multi-layer neural networks. We obtained at most 100% true positive rate with our proposed method.

In this paper, we propose a logic-testing based HT detection and classification method utilizing steady state learning. We first observe that HTs are hidden while applying random test patterns in a short time but most of them can be activated in a very long-term random circuit operation. Hence it is very natural that we learn steady signal-transition states of every suspicious Trojan net in a netlist by performing short-term random simulation. After that, we simulate or emulate the netlist in a very long time by giving random test patterns and obtain a set of signal-transition states. By discovering correlation between them, our method detects HTs and finds out its behavior. Experimental results demonstrate that our method can successfully identify all the real Trojan nets to be Trojan nets and all the normal nets to be normal nets, while other existing logic-testing HT detection methods cannot detect some of them.

Recently, due to the increase of outsourcing in IC design, it has been reported that malicious third-party vendors often insert hardware Trojans into their ICs. How to detect them is a strong concern in IC design process. The features of hardware-Trojan infected nets (or Trojan nets) in ICs often differ from those of normal nets. To classify all the nets in netlists designed by third-party vendors into Trojan ones and normal ones, we have to extract effective Trojan features from Trojan nets. In this paper, we first propose 51 Trojan features which describe Trojan nets from netlists. Based on the importance values obtained from the random forest classifier, we extract the best set of 11 Trojan features out of the 51 features which can effectively detect Trojan nets, maximizing the F-measures. By using the 11 Trojan features extracted, the machine-learning based hardware Trojan classifier has achieved at most 100% true positive rate as well as 100% true negative rate in several TrustHUB benchmarks and obtained the average F-measure of 74.6%, which realizes the best values among existing machine-learning-based hardware-Trojan detection methods.

Recently, the requirement for non-volatile memory on embedded systems has increased because they can be applied with normally-off and power gating technologies to. However, they have a lower endurance than volatile memories. When data is encoded as a write-reduction code appropriately, the endurance of non-volatile memory can be enhanced by writing the encoded data into the memory. We propose a highly effective write-reduction method for a multi-level cell (MLC) non-volatile memory focusing on the write-reduction code (WRC) as the optimal bit-write reduction method. The WRC can be applied only to single-level cell non-volatile memory. The proposed method generates a cell-write reduction code based on the WRC; the cell has multiple bits as the holdable data. Our proposed method achieves a cell-write reduction by 31.6% compared to the conventional method.

Recently, we face a serious risk that malicious third-party vendors can very easily insert hardware Trojans into their IC products but it is very difficult to analyze huge and complex ICs. In this paper, we propose a hardware-Trojan classification method to identify hardware-Trojan infected nets (or Trojan nets) using a support vector machine (SVM). Firstly, we extract the five hardware-Trojan features in each net in a netlist. Secondly, since we cannot effectively give the simple and fixed threshold values to them to detect hardware Trojans, we represent them to be a five-dimensional vector and learn them by using SVM. Finally, we can successfully classify a set of all the nets in an unknown netlist into Trojan ones and normal ones based on the learned SVM classifier. We have applied our SVM-based hardware-Trojan classification method to Trust-HUB benchmarks and the results demonstrate that our method can much increase the true positive rate compared to the existing state-of-the-art results in most of the cases. In some cases, our method can achieve the true positive rate of 100%, which shows that all the Trojan nets in a netlist are completely detected by our method.

This paper proposes a redesign technique which designs from untrusted netlists to trusted netlists. Our approach consists of two phases, detection phase and invalidation phase. The detection phase picks up suspicious hardware Trojans (HTs) by pattern matching. The invalidation phase modifies the suspicious HTs in order not to activate them. In the invalidation phase, three invalidation techniques are selected by analyzing location of suspicious malicious nets. Applying appropriately the invalidation technique to the nets can correctly invalidate HTs. In our results, the proposed technique can successfully invalidate HTs on several Trust-HUB benchmarks without HT activations. The results clearly demonstrate that our redesign technique is very effective to remove HT risks.

Power analysis for IoT devices is strongly required to reduce power consumption and realize secure communications. In this paper, we propose a scalable and small-sized power analyzer with signal-averaging noise reduction for low-power IoT devices. The proposed power analyzer reduces a wide frequency range of noises by using a signal averaging method and is implemented on just a 2cmx3cm board, which is the smallest size among the other existing power analyzers for IoT devices. It further has the following advantages: (a) It has a two-level amplifier that amplifies current signals adaptively depending on their magnitude. Hence maximum readable current can be increased with keeping minimum readable current small enough. (b) If long-time analysis is required, it can be partitioned into several analysis segments. The proposed power analyzer can measure currents and voltages of each analysis segment by using a small amount of data memories. After that, by combining these analysis segments using a timer module, we can obtain long-time analysis results. We have analyzed power and energy consumption of encryption processes of AES block cipher on the IoT device and demonstrated that the proposed power analyzer has only 1.8% measurement error compared with a high-precision oscilloscope.

Non-volatile memory has many advantages over SRAM. However, one of its largest problems is that it consumes a large amount of energy in writing. In this paper, we propose a bit-write reduction method based on error correcting codes for non-volatile memories. When a data is written into a memory cell, we do not write it directly but encode it into a codeword. We focus on error-correcting codes and generate new codes called write-reduction codes. In our write-reduction codes, each data corresponds to an information vector in an error-correcting code and an information vector corresponds not to a single codeword but a set of write-reduction codewords. Given a writing data and current memory bits, we can deterministically select a particular write-reduction codeword corresponding to a data to be written, where the maximum number of flipped bits are theoretically minimized. Then the number of writing bits into memory cells will also be minimized. We perform several experimental evaluations and demonstrate up to 72% energy reduction.

The recent development of network technologies that offer centralized control of explicit routes opens the door to the online optimization of explicit routing. For this kind of Traffic Engineering optimization, raising the calculation speeds by using multi-core processors with effective parallel algorithms is a key goal. This paper proposes an effective parallel algorithm for General purpose Programming on Graphic Processing Unit (GPGPU); its massively parallel style promises strong acceleration of calculation speed. The proposed algorithm parallelizes not only the search method of the Genetic Algorithm, but also its fitness functions, which calculate the network congestion ratio, so as to fully utilize the power of modern GPGPUs. Concurrently, each execution is designed for thread-block execution on the GPU with consideration of thread occupancy, local resources, and SIMT execution to maximize GPU performance. Evaluations show that the proposed algorithm offers, on average, a nine fold speedup compared to the conventional CPU approach.

Non-volatile memories are paid attention to as a promising alternative to memory design. Data stored in them still may be destructed due to crosstalk and radiation. We can restore the data by using error-correcting codes which require extra bits to correct bit errors. Further, non-volatile memories consume ten to hundred times more energy than normal memories in bit-writing. When we configure them using error-correcting codes, it is quite necessary to reduce writing bits. In this paper, we propose a method to generate a bit-write-reducing code with error-correcting ability. We first pick up an error-correcting code which can correct t-bit errors. We cluster its codeswords and generate a cluster graph satisfying the S-bit flip conditions. We assign a data to be written to each cluster. In other words, we generate one-to-many mapping from each data to the codewords in the cluster. We prove that, if the cluster graph is a complete graph, every data in a memory cell can be re-written into another data by flipping at most S bits keeping error-correcting ability to t bits. We further propose an efficient method to cluster error-correcting codewords. Experimental results demonstrate that, when we apply our bit-write-reducing code to MediaBench applications, it can reduce writing-bit counts by up to 28.2% and also energy consumption of non-volatile memory cells by up to 27.9% compared to existing error-correcting codes keeping the same error-correcting ability. This paper proposes the world-first theoretically near-optimal bit-write-reducing code with error-correcting ability based on the efficient coding theories.

As process technologies advance, interconnection delays are not negligible even in high-level synthesis and regular-distributed-register (RDR) architecture has been proposed to cope with this problem. In this paper, we propose a floorplan-driven high-level synthesis algorithm using multiple-operation chainings composed of two or more operations, and reduce the overall latency targeting RDR architecture. Our algorithm enumerates multiple-operation-chaining path candidates before performing scheduling/binding. Based on them, we find out optimal ones taking into account RDR floorplan information. Experimental results show that our algorithm successfully reduces the latency by up to 30.4% compared to the conventional approaches.

LED (Light Encryption Device) block cipher, one of lightweight block ciphers, is very compact in hardware. Its encryption process is composed of AES-like rounds. Recently, a scan-based side-channel attack is reported which retrieves the secret information inside the cryptosystem utilizing scan chains, one of design-for-test techniques. In this paper, a scan-based attack method on the LED block cipher using scan signatures is proposed. In our proposed method, we focus on a particular 16-bit position in scanned data obtained from an LED LSI chip and retrieve its secret key using scan signatures. Experimental results show that our proposed method successfully retrieves its 64-bit secret key using 73 plaintexts on average if the scan chain is only connected to the LED block cipher. These experimental results also show the key is successfully retrieved even if the scan chain includes additional some 4000 1-bit registers.

Interpolation is a technique that presumes a value between existing data, which is often used for image scaling and correction of distortion. Linear interpolation is one of the interpolation techniques which interpolates inbetween values by linearly connecting two known values. Also, bi-linear interpolation is one of interpolation techniques, which interpolates a value linearly from its four circumferences. Both of them are used practically in many cases. In this paper, we propose high-speed and small-sized linear and bi-linear interpolation circuits based on selector logics. The proposed linear and bi-linear interpolation circuits reduce carry propagation delays by using selector logics and then realize fast and small-sized circuits. We have implemented our linear interpolation circuit and bi-linear interpolation circuits in several ways and evaluated each of them. We can find out that a selector-based bi-linear interpolation circuit where its partial products are summed up by using the arithmetic operator saves its area by up to 42% and reduces its delay by up to 18% compared with a conventional design.

In this paper, a concurrent faulty clock detection method is proposed for crypto circuits against clock glitch based differential fault analysis (DFA). In the proposed method, a nonlogic buffer-based delay chain is inserted, and then by monitoring the delay along the delay chain, a possible clock glitch based DFA can be detected. Experimental results on an AES circuit show that the proposed method can successfully detect clock glitch based attacks, and the required area overhead is only 0.47% that is much smaller than previous works.

In this paper, we propose a partial redundant fault-secure high-level synthesis algorithm for RDR architectures, where we duplicate a part of the original CDFG and maximize its reliability under a timing constraint. Firstly, our algorithm allocates some new additional functional units to vacant spaces on RDR islands for recomputation and increases the number of duplicated operation nodes. Secondly, it minimizes the number of inserted comparator nodes through re-scheduling/re-binding the recomputation CDFG's nodes. As a result, we will obtain a scheduled/bound recomputation CDFG and renewed functional unit allocation with high reliability. Experimental results demonstrate that our algorithm improves reliability by up to 52% compared with the conventional approach.

Scan test is a powerful test technique which can control and observe the internal states of the circuit under test through scan chains. However, it has been reported that it's possible to retrieve secret keys from cryptographic LSIs through scan chains. Therefore new secure test methods are required to satisfy both testability and security requirements. In this paper, a secure scan design is proposed to achieve adequate security requirement as a countermeasure against scan-based attacks, while still maintain high testability like normal scan testing. In our method, the internal scan chain is divided into several sub chains, and the connection order of sub chains can be dynamically changed. In addition, how to decide the connection order of those sub chains so that it can't be identified by an attacker is also proposed in this paper. The proposed method is implemented on an AES circuit to show its effectiveness, and a security analysis is also given to show how the proposed approach can be used as a countermeasure against those known scan-based attacks.

In this paper, we first propose a huddle-based distributed-register architecture (HDR architecture), an island-based distributed-register architecture for multi-cycle interconnect communications where we can develop several energy-saving techniques. Next, we propose an energy-efficient high-level synthesis algorithm for HDR architectures focusing on multiple supply voltages. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, huddles, each of which is composed of functional units, registers, controller, and level converters, are very naturally generated using floorplanning results. By assigning high supply voltage to critical huddles and low supply voltage to non-critical huddles, we can finally have energy-efficient floorplan-aware high-level synthesis. Experimental results show that our algorithm achieves 45% energy-saving compared with the conventional distributed-register architectures and conventional algorithms.

Network-on-chip (NoC) architectures are emerged as a promising solution to the lack of scalability in multiprocessor systems-on-chips (MPSoCs). In this paper, we propose a novel BMNoC configuration algorithm together with simulation results. Our BMNoC configuration algorithm analyses the data traffic of the target application and determines which core is the right one to put into the certain cluster with its communication volume and locality. Furthermore, the simulation results illustrate the better latency than earlier studies and feasibility of BMNoC.

Scan technology carries the potential risk of being misused as a “side channel” to leak out the secrets of crypto cores. The existing scan-based attacks could be viewed as one kind of differential cryptanalysis, which takes advantages of scan chains to observe the bit changes between pairs of chosen plaintexts so as to identify the secret keys. To address such a design/test challenge, this paper proposes a robust secure scan structure design for crypto cores as a countermeasure against scan-based attacks to maintain high security without compromising the testability.

Scan-based attacks are techniques to decipher a secret key using scanned data obtained from a cryptography circuit. Public-key cryptography, such as RSA and elliptic curve cryptosystem (ECC), is extensively used but conventional scan-based attacks cannot be applied to it, because it has a complicated algorithm as well as a complicated architecture. This paper proposes a scan-based attack which enables us to decipher a secret key in ECC. The proposed method is based on detecting intermediate values calculated in ECC. By monitoring the 1-bit sequence in the scan path, we can find out the register position specific to the intermediate value in it and we can know whether this intermediate value is calculated or not in the target ECC circuit. By using several intermediate values, we can decipher a secret key. The experimental results demonstrate that a secret key in a practical ECC circuit can be deciphered using 29 points over the elliptic curve E within 40 seconds.

Scan test is a powerful and popular test technique because it can control and observe the internal states of the circuit under test. However, scan path would be used to discover the internals of crypto hardware, which presents a significant security risk of information leakage. An interesting design-for-test technique by inserting inverters into the internal scan path to complicate the scan structure has been recently presented. Unfortunately, it still carries the potential of being attacked through statistical analysis of the information scanned out from chips. Therefore, in this paper we propose secure scan architecture, called dynamic variable secure scan, against scan-based side channel attack. The modified scan flip-flops are state-dependent, which could cause the output of each State-dependent Scan FF to be inverted or not so as to make it more difficult to discover the internal scan architecture.

In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Functional units on a critical path use local registers and local controllers and functional units on non-critical path use shared register and global controller in our architecture. Our method is based on iterative improvement of scheduling/binding and floorplanning. Using iterative flow, we obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that 8.6% performance improvement can be achieved compared to the conventional high-performance method.

Due to the limitations of scan structure, the second vector in transition delay test is usually applied either by shift operation or by functional launch, which possibly results in unsatisfying transition delay fault (TDF) coverage. To overcome such a limitation for higher TDF coverage, a novel improved launch delay test technique that combines the pros of launch-on-shift and launch-on-capture tests is introduced in this paper. The proposed method can achieve near perfect TDF coverage with fewer test patterns without the need for a global fast scan enable signal. Experimental results on ISCAS89 and ITC99 benchmark circuits are included to show the effectiveness of the proposed method.

In recent years, the gap between the cycle time of processors and memory access time has been increasing. One of the solutions to solve this problem is to use a cache. But just using a large cache may not reduce the total memory access time. We can have an optimal cache configuration which minimizes overall memory access time by varying the three cache parameters: a cache set size, a line size, and an associativity. In this paper, we propose two exact cache simulation algorithms: CRCB1 and CRCB2, based on cache inclusion property. They realize exact cache simulation but increase simulation speed dramatically. By using our approach, the number of cache hit/miss judgments required for simulating all the cache configurations is reduced to 31.4% - 93.6% compared to conventional approaches. As a result, our proposed approach totally runs an average of 1.8 times faster and a maximum of 3.3 times faster compared to the fastest approach proposed so far. Our proposed exact cache simulation approach achieves the world fastest L1 cache simulation.

Scan technology carries the potential of being misused as a ¿side channel¿ to leak out the secret information of crypto cores. To address such a design challenge, this paper proposes a design-for-secure-test (DFST) solution for crypto cores by adding a stimuli-launched flip-flop into the traditional scan flip-flop to maintain the high test quality without compromising the security.

This paper introduces GECOM technology, a novel test compression method with seamless integration of test GEneration, test COmpression (i.e. integrated compression on scan stimulus and masking bits) and all unknown scan responses Masking for manufacturing test cost reduction. Unlike most of prior methods, the proposed method considers the unknown responses during ATPG procedure and selectively encodes the specified 1 or 0 bits (either is or Os) in scan slices for compression while at the same time masks the unknown responses before sending them to the response compactor. The proposed GECOM technology consists of GECOM architecture and GECOM ATPG technique. In the GECOM architecture, for a circuit with N internal scan chains, only c tester channels, where c = [log2N] +2, are required. GECOM ATPG generates test patterns for the GECOM architecture thus not only the scan inputs could be efficiently compressed but also all the unknown responses would be masked. Experimental results on both benchmark circuits and real industrial designs indicated the effectiveness of the proposed GECOM technique.

Modular multiplication is the most dominant arithmetic operation in elliptic curve cryptography (ECC), which is a type of public-key cryptography. Montgomery multiplication is commonly used as a technique for the modular multiplication and required scalability since the bit length of operands varies depending on the security levels. Also, ECC is performed in GF(P) or GF(2n), and unified architectures for GF(P) and GF(2n) multiplier are needed. However, in previous works, changing frequency or dual-radix architecture is necessary to deal with delay-time difference between GF(P) and GF(2n) circuits of the multiplier because the critical path of GF(P) circuit is longer. This paper proposes a scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). The proposed architecture unifies 4 parallel radix-216multipliers in GF(P) and a radix-264multiplier in GF(2n) into a single unit. Applying lower radix to GF(P) multiplier shortens its critical path and makes it possible to compute the operands in the two fields using the same multiplier at the same frequency so that clock dividers to deal with the delay-time difference are not required. Moreover, parallel architecture in GF(P) reduces the clock cycles increased by dual-radix approach. Consequently, the proposed architecture achieves to compute GF(P) 256-bit Montgomery multiplication in 0.23 mus.

Cryptography plays an important role in the security of data transmission. To ensure the correctness of crypto hardware, we should conduct testing at fabrication and infield. However, the state-of-the-art scan-based test techniques, to achieve high test qualities, need to increase the testability of the circuit under test, which carries a potential of being misused to reveal the secret information of the crypto hardware. Thus, to develop efficient test strategies for crypto hardware to achieve high test quality without compromising security becomes an important task. In this paper we discuss the development of a design-for-secure-test (DFST) technique for pipelined AES to overcome the above contradiction between security and test quality in testing crypto hardware. Unlike previous works, the proposed method can keep all the secrets inside and provide high test quality and fault diagnosis ability as well. Furthermore, the proposed DFST technique can significantly reduce test application time, test data volume, and test generation effort as additional benefits.

This paper proposes the power-efficient LDPC decoder architecture which features (1) a FIFO buffering based rapid convergence schedule which enables the decoder to accelerate the decoding throughput without increasing the required number of memory bits, (2) an intermediate message compression technique based on a clock gated shift register which reduces the read and write power dissipation for the intermediate messages. Simulation results show that the proposed decoder achieves 1.66 times faster decoding throughput, and improves the power efficiency (which is defined by the power dissipation per Mbps) up to 52% compared to the decoder based on the conventional overlapped schedule.

In SoC designs, efficient communication between the hardware IPs and the on-chip processor becomes very important; however the interface is usually affected by the processor core specification. Thus in this paper, we focus on developing an efficient interface circuit architecture for the communications between the on-chip processor and embedded hardware IP cores, we also propose a method to synthesize it. Experimental results show that our method could obtain optimal interface circuits and works well through designing a MPEG-4 encode application.

This paper proposes a new multiscan-based test input data compression technique by employing a fan-out compression scan architecture (FCSCAN) for test cost reduction. The basic idea of FCSCAN is to target the minority specified 1 or 0 bits (either 1 or 0) in scan slices for compression. Due to the low specified bit density in test cube set, FCSCAN can significantly reduce input test data volume and the number of required test channels so as to reduce test cost. The FCSCAN technique is easy to be implemented with small hardware overhead and does not need any special ATPG for test generation. In addition, based on the theoretical compression efficiency analysis, improved procedures are also proposed for the FCSCAN to achieve further compression. Experimental results on both benchmark circuits and one real industrial design indicate that drastic reduction in test cost can be indeed achieved.

This paper proposes a parallel LSI architecture for LDPC decoder which improves a message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) the column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently; and (ii) the proposed parallel pipelined bit functional unit enables the decoder to perform every column operation using the messages which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay. Hardware implementation and simulation results show that the proposed decoder improves the decoding throughput and bit error performance with a small hardware overhead

This paper proposes a reconfigurable adaptive FEC system with interleaving. For adaptive FEC schemes, we can implement an optimal RS decoder composed of minimum hardware units for any given error correction capability t. If the hardware units of the RS decoder can be reduced for any given t, we can embed as large deinterleaver as possible into the RS decoder for each t. Reconfiguring the RS decoder embedded with the expanded deinterleaver dynamically for each t allows us to decode larger interleaved codes which are more robust FEC codes to burst errors. Our reconfigurable adaptive FEC system with interleaving achieves better packet error rate and higher throughput than fixed hardware systems.

This paper proposes a new design methodology for SoCs reusing hardware IPs. In our approach, after system-level HW/SW partitioning, we use IPs for hardware parts, but synthesize a new processor core instead of reusing a processor core IP. System performs efficient parallel execution of hardware and software by taking account of a response time of hardware IP obtained by the proposed calculation algorithm. We can use optimal hardware IPs selected by the proposed hardware IPs selection algorithm. The experimental results show effectiveness of our new design methodology.

This paper presents a new DFT technique that can significantly reduce test data volume as well as scan-in power consumption for multiscan-based designs. It can also help to reduce test time and tester channel requirements with small hardware overhead. In the proposed approach, we start with a pre-computed test cube set and fill the don’t-cares with proper values for joint reduction of test data volume and scan power consumption. In addition we explore the linear dependencies of the scan chains to construct a fanout structure only with inverters to achieve further compression. Experimental results for the larger ISCAS’89 benchmarks show the efficiency of the proposed technique.

This paper proposes a partially-parallel LDPC decoder based on a high-efficiency message-passing algorithm. Our proposed partially-parallel LDPC decoder performs the column operations for bit nodes in conjunction with the row operations for check nodes. Bit functional unit with pipeline architecture in our LDPC decoder allows us to perform column operations for every bit node connected to each of check nodes which are updated by the row operations in parallel. Our proposed LDPC decoder improves the tuning when the column operations are performed, accordingly it improves the message-passing efficiency within the limited number of iterations for decoding. We implemented the proposed partially-parallel LDPC decoder on an FPGA, and simulated its decoding performance. Practical simulation shows that our proposed LDPC decoder reduces the number of iterations for decoding, and it improves the bit error performance with a small hardware overhead.

Test data volume and scan power are two major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce both test data volume and scan-in power consumption. The proposed method analyzes the compatibility of the internal scan cells for a given test set and then divides the scan cells into compatible classes. To extract the compatible scan cells we apply a heuristic algorithm by solving the graph coloring problem; and then a simple greedy algorithm is used to configure the scan chain for the minimization of scan power. Experimental results for the larger ISCAS'89 benchmarks show that the proposed approach leads to highly reduced test data volume with significant power savings during scan test.

This paper proposes a new hardware/software partitioning algorithm for processor cores with SIMD instructions. Given a compiled assembly code including SIMD instructions, a timing constraint of execution time, and available hardware units, the proposed algorithm synthesizes an area-optimized processor core with a new assembly code. Firstly, we assume an initial processor core on which an input assembly code can run with the shortest execution time. Secondly we reduce a hardware unit added to a processor core one by one while the timing constraint is satisfied. At the same time, we update the assembly code so that it can run on the new processor configuration. By repeating this process, we finally obtain a processor core architecture with small area under the given timing constraint. We expect that we can obtain a processor core which has appropriate SIMD functional units for running the input application program. The promising experimental results are also shown.

Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for processor kernel can be mainly obtained by minimum area for processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2% and errors of delay estimation are less than 2ns when comparing estimated area and delay with logic-synthesized area and delay.

Article Free Access Share on An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper) Authors: Nozomu Togawa Dept. of Electronics, Information and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, Japan Dept. of Electronics, Information and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, JapanView Profile , Masayuki Ienaga Dept. of Electronics, Information and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, Japan Dept. of Electronics, Information and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, JapanView Profile , Masao Yanagisawa Dept. of Electronics, Information and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, Japan Dept. of Electronics, Information and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, JapanView Profile , Tatsuo Ohtsuki Dept. of Electronics, Information and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, Japan Dept. of Electronics, Information and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, JapanView Profile Authors Info & Claims ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation ConferenceJanuary 2000 Pages 309–312https://doi.org/10.1145/368434.368652Online:28 January 2000Publication History 2citation93DownloadsMetricsTotal Citations2Total Downloads93Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A hardware/software cosynthesis system for processor cores of digital signal processing has been developed. This paper focuses on a hardware/software partitioning algorithm which is one of the key issues in the system. Given an input assembly code generated by the compiler in the system, the proposed hardware/software partitioning algorithm first determines the types and the numbers of required hardware units, such as multiple functional units, hardware loop units, and particular addressing units, for a processor core (initial resource allocation). Second, the hardware units determined at initial resource allocation are reduced one by one while the assembly code meets a given timing constraint (configuration of a processor core). The execution time of the assembly code becomes longer but the hardware costs for a processor core to execute it becomes smaller. Finally, it outputs an optimized assembly code and a processor configuration. Experimental results demonstrate that the system synthesizes processor cores effectively according to the features of an application program/data.

This paper proposes a high-level synthesis system for datapath design of digital signal processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.

Rapid system prototyping is one of the main applications for field-programmable gate arrays (FPGAs). At the stage of rapid system prototyping, design specifications can often be changed since they cannot always be determined completely. In this paper, layout design change is focused on and a layout reconfiguration algorithm is proposed for FPGAs. In layout reconfiguration, the main problem is to add LUTs to initial layouts. Our algorithm consists of two steps: For given placement and global routing of LUTs, Step 1 places an added LUT with allowing that the position of the added LUT may overlap that of a preplaced LUT; Then Step 2 moves preplaced LUTs to their adjacent positions so that the overlap of the LUT positions can be resolved. Global routes are updated corresponding to reconfiguration of placement. The algorithm keeps routing congestion small by evaluating global routes directly both in Steps 1 and 2. Especially in Step 2, if the minimum number of preplaced LUTs are moved to their adjacent positions, our algorithm minimizes routing congestion. Experimental results demonstrate the effectiveness and efficiency of the algorithm.

A new field programmable gate array (FPGA) design algorithm, Maple-opt, is proposed for technology mapping, placement, and global routing subject to a given upper bound of critical signal path delay. The basic procedure of Maple-opt is viewed as top-down hierarchical bipartition of a layout region. In each bipartitioning step, technology mapping onto logic blocks of FPGAs, their placement, and global routing are determined simultaneously, which leads to a more congestion-balanced layout for routing. In addition, Maple-opt is capable of estimating a lower bound of the delay for a constrained path and of extracting critical paths based on the difference between the lower bounds and given constraint values in each bipartitioning step. Two delay-reduction procedures for the critical paths are applied; routing delay reduction and logic-block delay reduction. The routing delay reduction is done by assigning each constrained path to a single subregion when bipartitioning a region. The logic-block delay reduction is done by mapping each constrained path onto a smaller number of logic blocks. Experimental results for benchmark circuits demonstrate that Maple-opt reduces the maximum number of tracks per channel by a maximum of 38% compared with existing algorithms while satisfying almost all the path delay constraints.

In the layout design of transport-processing FPGAs, it is not only required that routing congestion be kept small but also that circuits implemented on them should operate with higher operation frequency. This paper extends the proposed simultaneous placement and global routing algorithm for transport-processing FPGAs, whose objective is to minimize the routing congestion, and proposes a new algorithm, in which the length of each critical signal path (path length) is limited within a specified upper bound imposed on it (path length constraint). The algorithm is based on the hierarchical bipartitioning of the layout regions and LUT (lookup table) sets that are to be placed. Each bipartitioning procedure consists of three phases: (1) estimation of path lengths, (2) bipartitioning of a set of terminals, and (3) bipartitioning of a set of LUTs. After searching the paths with tighter path length constraints by estimating the path lengths in (1), phases (2) and (3) are executed so that their path lengths are reduced with higher priority, and thus path length constraints are not violated. The algorithm has been implemented and applied to transport-processing circuits and compared with conventional approaches. The results demonstrate that the algorithm resolves path length constraints for 11 out of 13 circuits, though it increases the routing congestion by an average of 20%. After detailed routing, it achieves 100% routing for all the circuits and reduces the circuit delay by an average of 23%.

No abstract available.

Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Mapleis an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic processes and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.

An FPGA layout algorithm is presented, which deals with placement and global routing simultaneously by fully exploiting its regular structure. It is based on a simple and fast top-down hierarchical bi-partitioning, with placement and global routes represented by positions of logic-blocks and pseudo-blocks, respectively. Experimental results for several benchmark circuits demonstrates its efficiency and effectiveness.>