Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Kanna Shimizu

dblp:94/1645 · DBLP profile ↗
← Back
6ranked-venue papers
3as first author
2since 2021 · last 2023
0009-0003-9908-0329ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorArtificial intelligence and machine learning · 1 · 1 since 2021Security and privacy · 1Software engineering, systems software and programming languages · 1 · 1 first-authorDatabases, data management, data science and information retrieval · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021Theory of computation · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 49% Processor architecture and microarchitecture · 28% Hardware accelerators and domain-specific architectures · 23%
Network and information security
1 paper
Hardware security and side channels · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test
0.122006
Verification of the cell broadband engineTM processor · DAC 2006
Deriving a simulation input generator and a coverage metric from a formal specification · DAC 2002
Hardware security and side channels
trusted execution environments
0.112009
Effective implementation of the cell broadband engineTM isolation loader · CCS 2009
Hardware accelerators and domain-specific architectures › many-core accelerator
cell broadband engine
0.112009
Effective implementation of the cell broadband engineTM isolation loader · CCS 2009
Processor architecture and microarchitecture › multicore design
heterogeneous multicore
0.112009
Effective implementation of the cell broadband engineTM isolation loader · CCS 2009
Electronic design automation › hardware verification and test
processor verification
0.112006
Verification of the cell broadband engineTM processor · DAC 2006
Electronic design automation › hardware verification and test
functional verification
0.012002
Deriving a simulation input generator and a coverage metric from a formal specification · DAC 2002
Processor architecture and microarchitecture
multicore design
0.012006
Verification of the cell broadband engineTM processor · DAC 2006

Methods — techniques the papers use, named apart from their topics

substituted-ciphertext attack countermeasure · 0.2SHA-1 · 0.2RSA-2048 · 0.2AES · 0.2formal specification · 0.0
YearPublicationVenuePosition
2023 Record Deduplication for Entity Distribution Modeling in ASR Transcripts
Chung Hoon Hong, Carl Wivagg, Kanna Shimizu
INTERSPEECH4
2023 RecQR: Using Recommendation Systems for Query Reformulation to correct unseen errors in spoken dialog systems
abstract
As spoken dialog systems like Siri, Alexa and Google Assistant become widespread, it becomes apparent that relying solely on global, one-size-fits-all models of Automatic Speech Recognition (ASR), Natural Language Understanding (NLU) and Entity Resolution (ER), is inadequate for delivering a friction-less customer experience. To address this issue, Query Reformulation (QR) has emerged as a crucial technique for personalizing these systems and reducing customer friction. However, existing QR models, trained on personal rephrases in history face a critical drawback - they are unable to reformulate unseen queries to unseen targets. To alleviate this, we present RecQR, a novel system based on collaborative filters, designed to reformulate unseen defective requests to target requests that a customer may never have requested for in the past. RecQR anticipates a customer’s future requests and rewrites them using state of the art, large-scale, collaborative filtering and query reformulation models. Based on experiments we find that it reduces errors by nearly 40% (relative) on the reformulated utterances.
Manik Bhandari, Mingxian Wang, Oleg Poliannikov, Kanna Shimizu
RecSys4
2009 Effective implementation of the cell broadband engineTM isolation loader
abstract
This paper presents the design and implementation of the Cell Broadband Engine TM(Cell/B.E.) isolation loader which is a part of the IBM Software Development Kit for Multicore Acceleration [14]. Our isolation loader is a key component in realizing secure application boot and encrypted application execution. During the application load process, the isolation loader fetches, validates, and decrypts a Synergistic Processor Element (SPE) executable, establishing a chain of trust from the hardware to the application. Since not all applications are SPE executables, we also introduce a general solution. This is a verification service framework in which all applications including system functions can be verified by the isolation loader immediately before execution.We have applied several novel implementation techniques to the isolation loader. The countermeasure implemented in our isolation loader against the substituted-ciphertext attack is given and our staging technique to allocate contiguous working areas for applications is also introduced. The load overhead of this loader including application fetch, validation (RSA-2048/SHA-1), and decryption (RSA-2048 and AES) is less than 50 milliseconds on the 2.8 GHz IBM PowerXCell 8i processor. This overhead is reasonable compared with the 500-millisecond 2048-bit RSA signing needed by the Trusted Platform Module chips [3].
Masana Murase, Kanna Shimizu, Wilfred Plouffe, Masaharu Sakamoto
CCS2
2006 Verification of the cell broadband engineTM processor
abstract
Successfully developing an implementation of entirely new chip architecture such as the Cell Broadband Engine (Cell BE) processor from scratch is a notable achievement.Consider further the design complexity (234 million transistors) and the project management complexity (5 participating companies, work in 5 different time zones), and the task seems quite challenging.This paper describes how the central verification team staffed by Sony Computer Entertainment Inc. (SCEI), Toshiba Corporation, and IBM, produced on first silicon a Cell BE microprocessor functional enough to boot an operating system and run applications.
Kanna Shimizu, Tatsuya Koyama, Takashi Omizo, Jamee Abdulhafiz, Larry McConville, Todd Swanson
DAC1
2002 Deriving a simulation input generator and a coverage metric from a formal specification
abstract
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a functional coverage metric are all created automatically from a single specification. Additionally, the process exploits the structure of a specification written with simple style rules. The methodology was used to verify a large-scale I/O design from the Stanford FLASH project.
Kanna Shimizu, David L. Dill
DAC1
2000 Monitor-Based Formal Specification of PCI
Kanna Shimizu, David L. Dill, Alan J. Hu
FMCAD1