Although innovations in manufacturing technology help in reducing variations, IC design variations are a fact of life. In addition to random variations, systematic stress induced variations are becoming increasingly important. This panel will bring the diverse views from academia, foundries, fabless and IDM communities to address various topics on next generation solutions for variability, with the main emphasis on design and architecture solutions. Specifically, this panel will discuss:• Would new architectures mitigate variability in 22nm and beyond?• Could design regularity effectively mitigate variability?• What design techniques can be used to minimize variability 'on-the-fly'?• What new techniques can be used for memories, register arrays and flip-flops?

Ultra low power and energy efficiency requirements are common to most IC designs today. Requirements range from extending battery life to operating on harvested energy, with applications ranging from consumer electronics to medical applications. Design methodologies have evolved over the past decade to cater to low power designs. This panel will discuss the design methodology challenges in the next generation ultra low power and energy efficient IC designs, covering EDA roadmap, low power standards, and design and verification flows.

Interconnect parasitics are playing a dominant role in determining chip performance and functionality in deep-submicron designs. This problem is compounded by increasing chip frequencies and design complexity. As parasitic coupling capacitances are a significant portion of total capacitance in deep-submicron designs, verification of both performance and functionality assumes greater importance. This paper describes techniques for the modeling and analysis of parasitic coupling effects for large VLSI designs. Analysis results from a controlled experimental setup are presented to show the need for accurate cell models. Results from application of these techniques on a lending edge Digital Signal Processor (DSP) design are presented. Accuracy comparison with detailed SPICE-level analysis is included.

Dominance of interconnect parasitics in impacting functionality, performance and reliability in deep sub-micron (DSM) designs is a well known topic. Reduced metal pitches, process variations, new materials for metallization/dielectrics emphasizes an increased need for an accurate and yet practical methodology for full-chip performance and reliability verification. This paper describes salient features of the methodology used for timing verification, interconnect modeling, coupling compensation, signal electromigration, power network analysis on power distribution networks. Results from the application of this methodology on TMS320C6201 and TMS320C6701 designed in 0.18 u technology are discussed.