Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurability was seldom studied. In most of the published work, the shuffle network between the log-likelihood ratio (LLR) memory and the check- node units (CNU) is predetermined and optimized for a specific code. However, the most of the modern wireless communication systems typically specify multiple code-rates, codeword lengths and sub-matrix sizes (for the QC-LDPC codes) to provide and guarantee quality-of-service (QoS) over challenging channel conditions. It is therefore desirable to define a reconfigurable decoder architecture that can support different parameters. This paper proposes an adaptive shuffling algorithm for QC-LDPC codes which together with the Benes network provides arbitrary cyclic shift for arbitrary submatrix size smaller than the input size of the Benes network. For the submatrix size larger than the Benes network input size, the proposed algorithm can be extended to obtain the cyclic shift in multiple stages. Compared with the direct implementation of m m-to-1 multiplexers, the proposed algorithm achieves significant savings on area and routing complexity.

We present a pipelined block-serial decoder architecture for structured LDPC codes, implementing the layered-mode belief-propagation. We introduce the concept of LLR-update and mirror memory to enforce a pipelined decoding schedule. The pipelined architecture improves the latency of the LDPC decoder by about 2x-3x and has negligible performance loss when implemented with clever layer scheduling. We also present a low-complexity check-node architecture suitable for block-serial processing and utilize the properties of the min approximation to significantly reduce the memory requirement. The proposed architecture is suitable for mobile devices with data-rates of tens of mbps

In this paper, we evaluate the performance of the receiver employing an iterative RLS-based data detection and channel estimation for the structured irregular LDPC coded MIMO-OFDM system. Using the EXIT chart analysis, the performance of the detector with various approximate decoding algorithms is analyzed.

In this paper we discuss an efficient design flow from Matlab® to FPGA. Employing Matlab for algorithm research and as system level language allows efficient transition from algorithm development to implementation. We show that integrating Matlab with HDL design tools such as HDL designer® and Precision-C® , an efficient design flow, suitable for rapid prototyping, can be obtained. The design flow accelerates process of algorithm development and simplifies test-bench formulation and verification process. The overall development time thus can be significantly reduced. We elaborate on the advantages and disadvantages of the design flow. It will be shown that Matlab based design flow generates functional specifications that are useful for RTL development.