This paper proposes an approach based on oversampling and noise-shaping mechanisms to mitigate the implementation complexity of variable delay lines for mixed-signal calibration of timing-skew mismatch in time-interleaving ADCs. The proposed technique pushes the error (introduced by increasing the delay steps) outside the operating frequencies. Our method is more appropriate for noise-shaping time-interleaved ADCs since they are band-limited. However, the proposed method permits the utilization of either the high-frequency or low-frequency zones. This approach avoids utilizing complex clock routing methods. Also, it does not restrict the number of sub-ADCs. The proposed method is verified by behavioral simulations with MATLAB/Simulink. The mean of the spurious-free dynamic range (SFDR) is respectively enhanced by 11.64 dB and 17.72 dB for the low-frequency and high-frequency zones.

This paper presents a high data rate wireline Discrete Multitone (DMT) transceiver capable of operating at 252 Gbps and higher for short range chip-to-chip and chip-to-module applications. The use of DMT allows for higher spectral efficiency than PAM SERDES systems, using similar bandwidth as proposed 224 Gb/s PAM-4 systems but achieves higher data rates. Data rates have improved over other published wireline DMT designs with the use of narrow sub-channels with both adaptive bit- and power-loading along with a combined transmit and receive side equalization. Simulation and measured results show that the transmit side pre-compensation has improved the BER by a factor of 104 at 250 Gb/s. The system is measured over a channel with a loss of 18 dB at 50 GHz, showing a data rate of 252 Gb/s with a BER of 10-6, and a data rate of 400 Gb/s with a BER of 10-2.

Sigma–delta ($\Sigma \Delta$) digital-to-analog converters (DACs) are commonly used to realize programmable dc voltage generators in built-in self-test (BIST) schemes, largely on account of their high linearity. Unfortunately, such$\Sigma \Delta $-DACs require large amounts of digital memory and a reconstruction filter with a large silicon area footprint. In this article, a segmented DAC architecture is proposed. The proposed architecture is realized using two sub-DACs, where both are$\Sigma \Delta $-based. This DAC provides two advantages: filter footprint size reduction and memory savings, thereby allowing for a simpler BIST solution. The benefits of using the segmented$\Sigma \Delta $-DAC are shown using two experimental prototypes. The first is an IC prototype design using the TSMC 65-nm CMOS technology. It will be shown that the IC achieves 12 bits of resolution from 1020 memory elements, whereas an unsegmented$\Sigma \Delta $-DAC uses 4095 elements to obtain the same resolution. This is about a 75% savings in memory elements. The segmented prototype occupies 0.5 mm2of silicon area, whereas the unsegmented design occupies 0.77 mm2for the same resolution. A 35% silicon area savings compared with its unsegmented counterpart. A second prototype implements the segmented$\Sigma \Delta $-DAC architecture using discrete components. The discrete prototype achieves 16 bits of resolution from 1020 memory elements, whereas the unsegmented counterpart uses 65 535 bits for the same resolution. This is a 98% saving in memory elements.

For next generation high speed optical coherent systems, digital pre-emphasis filters are essential as they can pre-compensate for the transmitter frequency response and mitigate receiver noise enhancement. However, the downside of using full pre-emphasis to completely pre-compensate for the low bandwidth transmitter is that it increases the signal peak-to-average power ratio (PAPR), thus posing a higher effective number of bits (ENoB) requirement for the digital to analog converter (DAC) and increases optical modulation loss. In this paper, we study the impact of partial pre-emphasis filters on signal PAPR and show how partial pre-emphasis reduces DAC ENoB requirements and MZM modulation loss. Our proposed scheme reduced the DAC ENoB requirement from 5 to 4.5 bits at the same implementation SNR. This enables a lower optical module power through the reduction of DAC and driver amplifier (DA) power. The experimental results, for single-pol case for a partial pre-emphasis filter, showed that the system bandwidth can be extended from 10GHz to 20GHz and tolerate a 6dB loss for a 0.4dBQ penalty factor, and a 0.8dB PAPR reduction.

A novel method to predict epilepsy seizures using a single iEEG (Invasive Electro Encephalogram) channel is presented in this paper. This method can potentially facilitate surgeries performed on epileptic patients by avoiding the insertion of grid or stripe electrodes. Both surgery complications and cost would become more acceptable. Also, using a single electrode would significantly reduce the computational effort and; consequently, the power consumption of the Bluetooth implant that will be designed in a later phase. Since epileptic seizures are characterized by a change in the EEG entropy, the signal is processed through a combination of linear and non-linear techniques to determine the seizure signature and to perform its prediction process. Nonlinear techniques allow therefore describing, in a suitable way, the output dynamics of the IEEG channel and then the different evolution stages of oscillatory states. Stability could be characterized by appropriate tools like Lyapunov exponent and phase diagramMoreover, we describe the proposed Bluetooth implant design to give more insight about how we process the seizure detection.

New charge-steering latches are proposed and simulated in 28nm FD-SOI CMOS for use in wireline transceivers. Three new latches demonstrate power savings of up to 40% when compared to conventional charge-steering latches. These latches achieve power savings through the addition of a switch in the pMOS cross-coupled pair which eliminates transistor power consumption when they are not required. All new latches demonstrate the ability to operate at data rates exceeding 28Gb/s, enabling a 56Gb/s SERDES when used in a half-rate architecture. Simulation results are also verified through analytical expressions.

This paper presents a coherent subsampling test system arrangement that can be configured to measure the intrinsic noise and jitter transfer characteristic response of a time-based channel. Such as a phase-locked loop using a sampling rate that is established based on the incoming signal bandwidth rather than the highest frequency contained in the measured signal. These test systems are applicable to a wide range of applications from RF to optical communication systems and can be constructed using off-the-shelf components. Experiments conducted on a Teradyne Flex tester are used to validate the proposed subsampling principles.

This paper presents a highly effective method for parallel hard fault simulation and test-specification development. The proposed method formulates the fault-simulation problem as a problem of estimating the fault value based on the distance between the output parameter distribution of the fault-free and the faulty circuit. We demonstrate the effectiveness and practicality of our proposed method by showing results on different designs. This approach, extended by parametric fault testing, has been implemented as an automated tool set for integrated circuit (IC) testing.

This paper presents a highly effective method for parallel hard fault simulation and test specification development. The proposed method formulates the fault simulation problem as a problem of estimating the fault value based on the distance between the output parameter distribution of the fault-free and the faulty circuit. We demonstrate the effectiveness and practicality of our proposed method by showing results on different designs. This approach extended by parametric fault testing has been implemented as an automated tools set for IC testing.

Process variation has forever been the major fail cause of analog circuits where small deviations in component values cause large deviations in the measured output parameters. This paper presents a new approach for parametric fault simulation and test vector generation. The proposed approach utilizes the process information and the sensitivity of the circuit principal components in order to generate statistical models of the fault-free and the faulty circuit. The obtained information is then used as a measurement to quantify the testability of the circuit. This approach, extended by hard fault testing, has been implemented as automated tool set for IC testing called FaultMaxx and TestMaxx.

The areas of analog circuit fault simulation and test generation have not witnessed the same degree of success as their digital counterparts. This is due mainly to the complexity of analog behavior and the lack of a fault mode. We present a new functional fault modeling technique called the perturbation fault model. The perturbation fault model is based on an estimation of the distance between the responses of the faulty and fault-free circuit and their distributions. The model allows fault abstraction of physical defects through structural fault modeling and perturbation estimation. The fault simulation technique uses a linear estimation of the faulty and fault-free output circuits. Techniques for fault observation and propagation are presented in order to build a hierarchical analog fault simulator.

In this paper, a complete functional testing of embedded ADC is presented. The integral non-linearity error, INLE, differential non-linearity error, DNLE, offset error, OSE, gain error and the signal-to-noise ratio, SNR are rested. The problem related to the propagation of the analog signal to the input of the ADC and the observation of the digital output of the converter at the output of the digital circuit are discussed. The two means for functional testing are discussed: the histogram and the FFT. To observe the outputs of the ADC at the digital circuit, the inverse function of the digital circuit is computed. This can be done by inverting the transfer function of the digital circuit whenever it is available. In the other case, when the digital circuit structure is available, the inverse of the digital circuit is found by boolean function manipulation.

Integrating design and test presents a good challenge in today's analog circuit manufacturing process. Designs should be made according to the sensitivity of the output to all the components. Furthermore, sensitivity can be used to observe component deviation (soft faults) and hard faults from the output. This paper presents an automated sensitivity analysis tool, called LIMSoft, which offers the possibility of sensitivity computation and analysis in order to design fault-resistant circuits and generate test vectors for both soft and hard faults. Some applications for integrating test and design are also presented.

In this paper, a new approach to high-level synthesis testability evaluation is introduced. This approach consists of two phases: abstraction and propagation. In the abstraction phase, the function's primitive testability measures are abstracted from their oBDD representation. Then, the testability measure is propagated to evaluate data path testability and used in the synthesis for testability process. The choice of a testable design and the modification of a data flow during or after the scheduling and allocation phases are shown to be efficient.>

In this paper, a pseudo-random vector compaction technique for sequential circuits is presented. This technique is based on sequential testability measures and the iterative model. The optimum number of circuit duplications is deduced from the testability analysis. The pseudo random vector compaction consists of conserving the vectors that detect faults and the n-1 previous vectors, where n is the optimum number of circuit duplications. The results indicate that fault coverage produced by 200000 pseudo-random vectors is exactly reproduced by a small set of vectors which do not exceed 1000 vectors for almost all the benchmark circuits.>

Analog circuit testing is considered to be a very difficult task, due mainly to the lack of fault models and accessibility to internal nodes. An approach is presented for analog circuit modeling and testing to overcome this problem. This circuit modeling is based on a sensitivity computation and on circuit structure, which are crucial in analog circuit testing. The testability of the circuit is achieved for the simple fault model and by functional testing. Component deviations are deduced by measuring a number of output parameters, and through sensitivity analysis and tolerance computation. Using this approach, adequate tests are identified for testing both catastrophic and soft faults. Some experimental results are presented.>