This paper presents a hybrid step-up converter with only one inductor and one flying capacitor. The proposed converter features a left-half-plane zero rather than a right-half-plane one. With a broad bandwidth up to a tenth of the switching frequency, the converter can attain a fast transient response as a buck converter. In addition, the voltage conversion ratio of the proposed converter is identical to that of the conventional boost converter, thereby enabling a wide range of output voltage in systems powered by lithium-ion batteries. Measurement results demonstrate that a peak efficiency of 95.1% is obtained. Given a load current stepping from 50 mA to 500 mA in less than 160 ns, the settling time is merely $2.8 \mu \mathrm{~s}$.

This paper presents a $\mathbf{2 M H z}$ relaxation oscillator (ROSC) designed for ultra-low power internet-of-things (IoT) applications. Dynamic comparator with dual slope booster (DSB) is utilized to decrease the output jitter of oscillating frequency. A feedback loop with cascaded floating inverter amplifier (C-FIA) is adopted such that (1) the requirement of comparator speed is significantly alleviated and (2) the power consumption of the amplifier is further reduced. The proposed ROSC was fabricated in a 180 nm CMOS process and occupies only $0.1 \mathrm{~mm}^{2}$ active area. The measurement results with 8 samples show that the average power consumption is only $2.93 \mu \mathrm{~J} /$ cycle $(\mu \mathrm{W} / \mathrm{MHz})$ at 1 V supply voltage at room temperature. The average standard variation of the period jitter is 345 ps, which is as low as 0.068% of the 500 ns typical oscillation period (Tosc).

This paper proposes convergence enhancement to state-space averaging (SSA) methodology for steady-state and small-signal analysis of high-ratio hybrid DC-DC converters, first using analysis of Double-Step-Down (DSD) topology, including parasitics, as an example, then extending to other hybrid topologies with different numbers of capacitors and inductors. The enhanced SSA method can be used to:1)derive small-signal control-to-output transfer functions, which is essential to optimize the compensator for fast and stable closed-loop operation;2)calculate steady-state inductor currents, output voltage, input current and the voltage(s) across the flying capacitor(s),$V_{CFs}$, which is important to determine steady-state characteristics and performance;3)include circuit non-idealities such as parasitics and timing mismatches; and4)evaluate$V_{CF}$balancing property by the proposed matrix invertibility principle and added constants, and determine whether dedicated$V_{CF}$balancing circuits can be eliminated, which is considered an important benefit with reduced complexity and improved reliability. The theoretical results of DSD are then plotted in MATLAB and verified in simulations using PSIM and Cadence periodic transfer function (PXF) analysis, and measurement results using GaN devices. The simulation and measurement results match well with theoretical analysis. The enhancement is then extended beyond the DSD topology to analyze emerging hybrid topologies with more switched inductors and capacitors, future-proofing its capability to be applicable to new hybrid topologies.

This article presents a dual-phase hybrid dc—dc converter (DPHC) for the applications of high voltage conversion ratio and high output current delivery. The power stage topology evolved from the tri-state double step-down (DSD) topology by inserting a single additional power switch and a flying capacitor. Unlike conventional multi-phase converters that require equal inductor current sharing among all phases, the proposed converter allows intentionally unequal current distribution, which reduces current stress on specific components and improves overall efficiency. Additionally, all the flying capacitor voltages ($V_{{CF}}$) of the proposed DPHC are self-balanced during steady-state operation, cutting down the requirement for the circuit design for$V_{CF}$calibration. The proposed DPHC retains the characteristics of some other existing multi-level multi-phase hybrid topologies with fewer components. A PCB prototype is built to verify the performance of the proposed DPHC. Experimental results show that the peak efficiencies of the proposed DPHC are 94.6% and 91.1% respectively for the voltage conversion of 24 V/48 V to 1 V.

This paper presents a hybrid boost converter with a feature of “always’ reduced inductor current, enabling the usage of a low-profile inductor with high dc resistance (DCR) without compromising the power efficiency. The proposed boost converter also features a wide range of voltage conversion ratios as the conventional boost converter (CBC). Additionally, the output current of the proposed boost converter can be delivered continuously, and thus the output voltage ripple magnitude is reduced. Detailed dc analysis and small-signal modeling of the proposed converter are also included in this paper. Simulation results show that the average inductor current of the proposed boost converter can be greatly reduced compared with the CBC. The peak efficiency of 96.3% is achieved when an inductor with DCR of 250 mΩ is used.

This paper presents a monolithic single-stage, 4-phase switched-capacitor (SC) hybrid boost converter with 11-to-$20\times $voltage conversion ratios (VCRs). The 4-phase operating SC hybrid topology is proposed to achieve high VCRs with only three flying capacitors and one inductor. With the SC topology, the average inductor current and the inductor current ripple are much reduced, releasing both power loss and size requirement for the inductor. A four-phase pulse width modulation (PWM) controller is proposed. A successive ramp generation scheme ensures identical pulse widths across three consecutive phases. A driver-assisted auxiliary charge pump provides sufficient driving voltages for the high-side driver and simplifies the overall circuitry. The proposed hybrid boost converter was implemented in a$0.18~\mu $m process. The measurement results show that the converter achieved a 20-24V output voltage range with a 1.2-1.8 V input voltage. 76.7% peak efficiency was achieved at$13\times $VCR and power density was 12 mW/mm3.

This paper presents a 2MHz relaxation oscillator designed for ultra-low power internet-of-things (IoT) applications. Dynamic comparator with dual slope booster (DSB) is utilized to decrease the output jitter of oscillating frequency. A feedback loop with cascaded floating inverter amplifier (FIA) is adopted such that 1) the requirement of comparator speed is significantly alleviated and 2) the power consumption of the amplifier is further reduced. The proposed relaxation oscillator was fabricated in a 180nm CMOS process and occupies only 0.1mm2active area. The measurement results with 8 samples show that the average power consumption is 2.93μJ/cycle (μW/MHz) at 1V supply voltage at room temperature. The average standard variation of the period jitter is 345ps, which is 0.068% of 500ns typical oscillation period (TOSC). The measured temperature coefficient is 128ppm/∘C within the 0 to 90∘C range, and the voltage variation is 0.74%/0.1V from 0.95V to 1.15V. It scores a high phase noise figure-of-merit of 148dBc/Hz at 10kHz offset frequency.

A fully integrated single-input dual-output switched-capacitor converter with dynamic power-cell allocation for application processors is presented in this summary. The power cells can be dynamically allocated according to the loads, and the efficiency is improved by 4.8%. A dual-path voltage-control oscillator (VCO) that works independently of the power-cell allocation is proposed to achieve a fast and stable regulation loop. The converter achieved peak efficiency of 83.3% and maximum combined load-currents of 100mA while maintaining minimized cross regulation.

A systematic analysis of 3-level integrated buck converters is conducted in this paper. Detailed derivations of the working principles, voltage conversion ratio and output voltage ripple are given. In particular, the system loop gain of 3-level buck converters is analyzed, which provides guidance on designing fast and robust 3-level converters. The derived loop gain is verified with time-domain small signal injection analysis. The results show a good match between analytical and simulation results.