American Sign Language (ASL) has drawn growing attention due to its extensive application potential. This brief presents an ultralow-power real-time high-accuracy ASL recognition system (LRASL) for smart edge devices. It balances accuracy and power efficiency via a six-stage advanced hand region segmentation engine (AHRSE) and a hardware-sharing hierarchical self-similar binarized neural network engine (HSBNNE). The AHRSE compresses$640\times 480$RGB565 inputs into$32\times 32$binary gestures through six-stage processing, achieving a$4800\times $reduction in size, and boosting HSBNNE accuracy by 1.3%. Notably, similar gestures persist in binarized ASL gestures after extraction, increasing recognition difficulty and elevating hardware’s power consumption/resource demands. To address this, a novel miniaturized hierarchical self-similar binarized neural network (HSBNN) model with shared layers and dual self-similar expert branches is proposed. The HSBNNE, built on the HSBNN model, recognizes ASL gestures (similar and dissimilar ones) from coarse to fine, which achieves 95.8% recognition accuracy with only 3.96 MOPs and 2.86 KB parameters. The self-similar expert branches enable maximal reuse of hardware resources, reducing hardware overhead and lowering power consumption. Implemented in TSMC 28-nm CMOS, the proposed LRASL achieves a power consumption of only$45.2~\mu $W and a latency of 33.3 ms when operating at an 800-kHz clock frequency and 0.6-V supply voltage.

The limitations of the von Neumann architecture in terms of power consumption and throughput are increasingly evident. In-memory computing is a promising computing paradigm to alleviate this limitation. This article proposes a high-speed and low-power 10T compute-static random-access memory (CSRAM) capable of conducting rowwise search operations and executing in-memory logic functions efficiently. A self-suppressed discharge scheme is implemented to curtail the power consumption of the search operation by reducing the discharge swing of the match lines (MLs). The rowwise search scheme avoids vertical data storage, enhancing the compatibility between different operation modes. The proposed 10T SRAM architecture addresses the issue of sneak currents effectively when multiple lines are activated. Additionally, decoupled read ports eliminate compute access disturbance. To validate the design, a 4Kb array is designed with a 40-nm CMOS technology. At a supply voltage (VDD) of 1.1 V, the in-memory logic operations are capable of operating at a frequency of 752 MHz, consuming 29.2 fJ/bit. In binary content-addressable memory (BCAM) search mode, the minimum energy consumption of 0.51 fJ/bit occurs at 0.8 V and 120 MHz.

With SRAM-based computing in-memory (CIM), parallel searching is implemented through the multi-row activation scheme, which necessitates words to be stored in the column-wise fashion. However, existing column-wise write schemes usually require multi-cycle and cause write performance degradation for the SRAM with only row access transistors. In this study, we propose a novel 10T SRAM with both row and column access transistors, supporting data writing across row and column without additional data moving, overcoming the above problem. Furthermore, the proposed SRAM features horizontal and vertical read ports to enable two-direction logic operations, search operation, and matrix transposition, significantly enhancing computational flexibility. Besides, the array can be used to perform arithmetic operations. The 10T SRAM design is validated in a 4 Kb array with a 40-nm CMOS technology. It achieves a frequency of 917 MHz at 1.1V for logic operations. For binary content-addressable memory (BCAM) search operations, the energy consumption is 0.82 fJ/search/bit at 0.7 V in the worst case, and the frequency is up to 807 MHz at 1.1V.

In background subtraction tasks, spatial and temporal contexts are beneficial in detecting moving objects. The methods based on Deep Neural Networks in this task has explored different topologies, which are composed of the conventional operations of convolutional neural networks, such as Convolutional Long-short Term Memory layer (ConvLSTM), 2D convolutional layer, or 3D convolutional layer, to capture these contexts. In this work, we propose a new background subtraction algorithm named spatial–temporal propagation network. An end-to-end network with novel layers, whose process of operation is equivalent to that the feature maps multiply with affinity matrices, is proposed to capture the spatial–temporal correlation in video sequences and aggregate the deep features from the consecutive frames. Experimental results on CDnet-2014 and LASIESTA datasets show that this novel layer provides an alternative way for our network to aggregate multiscale spatial–temporal features. Meanwhile, the proposed network achieves state-of-the-art performance and is generalizable to unseen videos.

This brief proposes an ultralow-voltage four-read-port and two-write-port multiported register file with a novel architecture of read word-line sharing strategy for energy/area efficiency. Static read circuits and memory cells with nonminimum channel length are introduced to improve the ultralow-voltage performance. The chip of this register file is fabricated in 65-nm LP CMOS process and occupies the area of 0.019 mm$^{2}$ . Test results show that the minimum operation voltage is 320 mV with its corresponding max frequency 110 KHz. The minimum energy consumption is 0.94 pJ/cycle at the point of 400 mV, 850 KHz, corresponding to 0.15 fJ/port/bit/cycle after normalization. Compared with the state-of-the-art designs, it improves energy efficiency by 25% and saves the area by 58.7%.