Demo Data from EDBT 2026 / reviewers in the wild / expert
Masato Kitakami
dblp:94/2966
· DBLP profile ↗
19ranked-venue papers
8as first author
0since 2021 · last 2019
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 14 · 6 first-authorSoftware engineering, systems software and programming languages · 13 · 6 first-authorDatabases, data management, data science and information retrieval · 2 · 2 first-authorGraphics, computer vision, multimedia, augmented reality and games · 2 · 2 first-authorTheory of computation · 2Systems, architecture and hardware · 1Human-computer interaction and ubiquitous computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
2 papers |
Coding theory · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware reliability and fault tolerance · 82% Memory systems · 18% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware reliability and fault tolerance
error detection and correction |
0.0 | 1 | 1998 | Optimal Two-Level Unequal Error Control Codes for Computer Systems · IEEE Trans. Computers 1998 |
Coding theory
error-correcting codes |
0.0 | 1 | 1998 | Optimal Two-Level Unequal Error Control Codes for Computer Systems · IEEE Trans. Computers 1998 |
Hardware reliability and fault tolerance
memory fault tolerance |
0.0 | 1 | 1994 | A class of error-correcting codes for byte-organized memory systems · IEEE Trans. Inf. Theory 1994 |
Coding theory › error-correcting codes › burst error correction › byte error-correcting codes
byte-organized memory code |
0.0 | 1 | 1994 | A class of error-correcting codes for byte-organized memory systems · IEEE Trans. Inf. Theory 1994 |
Coding theory › error-correcting codes › error detection
error-locating codes |
0.0 | 1 | 1994 | A class of error-correcting codes for byte-organized memory systems · IEEE Trans. Inf. Theory 1994 |
Memory systems › memory architecture
byte-organized memory |
0.0 | 1 | 1994 | A class of error-correcting codes for byte-organized memory systems · IEEE Trans. Inf. Theory 1994 |
Memory systems
semiconductor memory |
0.0 | 1 | 1994 | A class of error-correcting codes for byte-organized memory systems · IEEE Trans. Inf. Theory 1994 |
Methods — techniques the papers use, named apart from their topics
decoder complexity analysis · 0.0code construction · 0.0linear code design · 0.0decoding hardware evaluation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2019 | A Method for Stable Block Generation Time in Proof of WorkabstractProof of Work, which is one of consensus algorithms in cryptocurrency, is used to decide the block creator for blockchain. The generation interval is unstable and a large delay often occurs. This paper proposes a method to stabilize block generation time by dividing blockchain. Computer simulations say that when applied to Bitcoin and Monacoin, the proposed method can reduce the block generation time to 1/4 and 1/9 respectively. Naoki Torii, Masato Kitakami |
PRDC | 2 |
| 2018 | An Attack-Tolerant Agreement Algorithm for Block ChainabstractThis paper proposes a method to protect block chains, which is transaction records in virtual currency such as Bitcoin, from majority voting attacks. In the proposed method, it is difficult to acquire consecutive blocks by increasing the difficulty level of the search problem for the node that acquired the block. Masato Kitakami, Kazuki Matsuoka |
PRDC | 1 |
| 2018 | Research on Convolutional Codes are Used in RAIDabstractThis paper proposes a new class of convolutional codes that are used in RAID, and compares their tolerating capabilities with existing MDS codes, they can solve erasure situations that the existing MDS codes of the same rate fail to solve for RAID. Masato Kitakami |
PRDC | 2 |
| 2016 | The effective method of improving Berlekamp-Preparata convolutional codes decoding by tail-biting technology
Masato Kitakami |
ISITA | 2 |
| 2014 | Codes Correcting Asymmetric/Unidirectional Errors along with Bidirectional Errors of Small MagnitudeabstractDominant error sources in multi-level cell NAND Flash memories shift threshold voltage levels to either positive or negative values, thus errors are modeled by nonbinary unidirectional channels. However, bidirectional errors can also be caused when positive and negative errors have equivalent significance. Compared to unidirectional cases, error magnitude of bidirectional errors are considered to be small. In this correspondence, novel error correcting codes which correct limited magnitude asymmetric/unidirectional errors along with bidirectional errors of relatively small magnitude are presented. They can be used to reduce encoding and decoding complexity compared to conventional symmetric error correcting codes. Shohei Kotaki, Masato Kitakami |
PRDC | 2 |
| 2013 | A Class of q-Ary Unidirectional Error Correcting Codes for MLC Flash MemoriesabstractError correcting codes (ECCs) are essential techniques to ensure reliability of NAND Flash Memories. BCH codes, ECCs which have been employed for multi-level cell (MLC) memories, don't reflect nonbinary error characteristics while error sources show them actually. Cell-to-cell interference (CCI), which occurs on a word unit, shifts threshold voltage distribution to the negative side. In addition, data retention, every cell suffers its effects, shifts the distribution to the positive side. Consequently, errors are either to upper levels, or lower levels in a word. Such errors, their values as an integer are either (+1) or (-1), can be regarded as unidirectional errors on q-ary symbols. This paper proposes codes capable of correcting the q-ary unidirectional errors. Evaluation results show the codes have less check bits than conventional BCH codes. Shohei Kotaki, Masato Kitakami |
PRDC | 2 |
| 2011 | Comparing Static Load Balancing Algorithms in Grid
Sherihan Abu Elenin, Masato Kitakami |
CDVE | 2 |
| 2011 | Error Recovery Method for PPM Compressed DataabstractSummary form only given. This paper proposes error recovery method for PPM. The proposed method is based on Static PPM, which has partial decoding capability, and divide the source data into blocks. Errors in the block are detected by checking the synchronization symbol which is inserted at the end of each block before compression. Erroneous block is recovered by parity block. Masato Kitakami, Tomoya Ebihara |
DCC | 1 |
| 2010 | Quantitative Evaluation of Integrity for Remote System Using the InternetabstractRecently, the number of remote systems using the Internet has been increased and the services provided by such systems get various. They are required to have high dependability. The existing evaluations have some problems. For example, the evaluations based on RASIS are vague and those provided by Japanese government are very complicated. The existing evaluations are not uniformed, not understandable, and not quantitative. Especially, quantitative metric of integrity has not been proposed yet. This paper proposes quantitative metric for integrity for remote systems based on the Internet. It is also useful for evaluation of the effect of the measure against data destruction elements. This paper applies it to example systems in order to confirm its effectiveness. Masato Kitakami, Hiroshi Konno, Kazuteru Namba, Hideo Ito |
PRDC | 1 |
| 2009 | Lossless Image Compression by PPM-Based Prediction CodingabstractLossless image compression, such as JPEG-LS and CALIC, are necessary for medical image and art work image archive, which has been processed by computers recently. Most of the conventional lossless image compressions are based on prediction compression which predicts the value of current symbol by using several symbols which have already been encoded. The difference between the predicted values and the actual values, called prediction error, is encoded by entropy coding independently. This paper proposes lossless image compression which is also based on prediction coding and the prediction errors are encoded by modified PPM (prediction by partial matching). Masato Kitakami, Kensuke Tai |
DCC | 1 |
| 2009 | Dependability Evaluation for Internet-Based Remote SystemsabstractRecently, the number of remote systems using the Internet has been increased and the services provided by such systems get various. They are required to have high dependability. The existing evaluations have some problems.For example, the evaluations based on RASIS are vague and those provided by Japanese government are very complicated. The existing evaluations are not uniformed, not understandable, and not quantitative. This paper proposes security evaluation metric which is a part of RASIS for remote systems using the Internet.The proposed metric gives quantitative evaluation in the similar manner of availability evaluation.It is based on the time that the system can tolerate take-over attack, which is one of the biggest threats among the attacks through the Internet.It can give appropriate system parameters to achieve the desired security.This paper applies it to example systems in order to confirm its effectiveness. Masato Kitakami, Akihiro Katada, Kazuteru Namba, Hideo Ito |
PRDC | 1 |
| 2007 | Error Recovery Method for Multiple-Dictionary Compression MethodabstractData compression is popularly applied to communication systems and computer systems. Ziv-Lempel coding is a class of popular data compression method and uses dictionary which includes the tendency of the source data. The dictionary is classified into two types, dictionary including local tendency of the source data and the one including global tendency of the source data. The compressed data have a problem that they are very sensitive to errors; and therefore, several error recovery methods for data compression have been proposed. This paper proposes error recovery method for data compression method which uses two types of dictionaries. The compression method is proposed by the authors and uses both local and global tendency of the source data. Computer simulations shows that compression ratio of the proposed compression method is better than existing Ziv-Lempel coding and its variations. Error recovery capability of the proposed code is high and the influence of the error is almost less than 10 percent. Masato Kitakami, Yuta Noguchi |
PRDC | 1 |
| 2005 | Code Design and Decoding Methods for Burst Error Locating CodesabstractError locating code, a class of error control codes, can indicate the location of the error and is useful to fault diagnosis in computer systems and reduction of the retransmission cost in communication systems. The authors proposed two types of burst error locating codes called B/sub 1/EL codes and SEC-B/sub 1/EL codes. Since single-hit errors are more probable than burst errors, the latter codes having single-bit error correction capability are practical. However, the code length of the existing SEC-B/sub 1/EL code is not long. This paper proposes efficient SEC-B/sub 1/EL codes having longer code length. The proposed code is obtained from a parity check matrix of burst error connecting codes. The number of the frames in the proposed SEC-B/sub 1/EL codes increases as the codelength increases, while that in the existing SEC-B/sub 1/EL codes infixed. This also proposes both parallel and serial decoding methods of the proposed code in order to apply this code to both computer and communication systems. The parallel decoder is implemented by hardware description language and its circuit area is evaluated. Code evaluation says that the code length of the proposed code is about 1.1 times as long as that of the existing code and that decoder circuit area of the proposed code is 20 to 40 percent of that of burst error correcting Fire code. Masato Kitakami, Junpei Sano |
PRDC | 1 |
| 2004 | Fault-Tolerant Message Switching Based on Wormhole Switching and BacktrackingabstractParallel computers are now popularly applied to applications where many calculations are required. In a NO Remote memory Access model (NORA) parallel computer, many processors are connected by communication links and calculation results are obtained by communications among processors. The message switching method, which controls message transmission in the parallel computer, is one of the most important parameters to improve the performance of the parallel computer. Since parallel computers include many processors, its failure rate is very high and many fault-tolerant switching methods have been proposed. The existing methods have problems, however, such as low communication throughput, low fault-tolerant capability, and large hardware overhead. We propose fault-tolerant switching by improving wormhole switching. The proposed method inserts dummy flits, having no information, after the header flit, the first flit of the packet. By overwriting the header flit to the dummy flit, backtracking is implemented without hardware overhead. Computer simulation says that in a 16 by 16 2D torus, for example, the throughput of the proposed method is almost equal to that of existing methods which require large hardware overhead if the number of the faulty nodes is less then 40. Manabu Sueishi, Masato Kitakami, Hideo Ito |
PRDC | 2 |
| 2002 | Fault-Tolerant Properties of Generalized Hierarchical Completely-Connected NetworksabstractAs a network topology for a massively parallel computer system, generalized hierarchical completely-connected networks (HCC), which include conventional hierarchical networks, have been proposed. To apply an HCC to a parallel computer system effectively and to execute data processing on the HCC efficiently, the inherent fault-tolerant properties in the HCC must be revealed. However, the properties have not been clarified enough. In this paper, the properties, such as node-connectivity, node-disjoint paths or container, and wide/fault diameter, are verified for the HCC. The concept of the block-connectivity related to the node-connectivity of HCC is introduced, and the fault-tolerance of HCC is discussed. Furthermore, to clear those properties of HCC the unknown properties of other hierarchical networks are also cleared. As a result, the HCC has a fault-diameter that is about 1.5 times as long as the diameter of HCC. Toshinori Takabatake, Masato Kitakami, Hideo Ito |
PRDC | 2 |
| 2001 | Fault-Tolerance of Functional Programs Based on the Parallel Graph ReductionabstractRecently, parallel computing has been applied to many systems. Functional programming is suitable for parallel programming because of referential transparency and is applied to symbol processing systems and parallel database systems. Programs with some functional programming can be regarded as graphs and are processed in terms of reduction of the corresponding graph. The paper proposes fault tolerance of functional programming based on graph reduction. The proposed method stores the received graph as a message log and an erroneous task is recovered by using the checkpoint and the stored graph. Computer simulations reveal that the time overhead of the proposed method is small. If the checkpoint interval is 30 seconds and the number of tasks is 3, for example, the time overhead is less than 10%. Masato Kitakami, Shunji Kubota, Hideo Ito |
PRDC | 1 |
| 2001 | Escape and Restoration Routing: Suspensive Deadlock Recovery in Interconnection NetworksabstractA routing strategy for suspensive deadlock recovery called an escape-restoration routing is proposed and its performance is evaluated. In the principle of the proposed techniques, a small amount of exclusive buffer (escape-buffer) at each router is prepared for handling one of the deadlocked packets. The transmission of the packet is suspended by temporarily escaping it to the escape-buffer. After the other deadlocked packets were sent, the suspended transmission resumes by restoring the escaped packet. Evaluation results show that the proposed techniques can improve the routing performance more than that of previous recovery-based techniques in handling deadlocks. Toshinori Takabatake, Masato Kitakami, Hideo Ito |
PRDC | 2 |
| 1998 | Optimal Two-Level Unequal Error Control Codes for Computer SystemsabstractError control codes are now successfully applied to computer systems and communication systems. When we consider some types of computer words or communication messages, the information in some part of the word is more important than the other. Address and control information in computer words and communication messages and pointer information in database words are good examples. The more important the part of the word is, or the less reliable the part is, the more strongly it should be protected from errors. Based on this, this paper proposes a new class of codes, called unequal error control codes, which have some unequal error control levels in the codeword, that is, have some distinct code functions in the codeword and protect the part of the word from errors according to its importance or reliability level. From a simple and practical viewpoint, this paper adopts the model of the codeword which includes two unequal levels: one having strong error control level in some part of the codeword, called fixed-byte, and the other having relatively weak error control level outside the fixed-byte. This paper deals with three basic unequal error control codes. For all types of codes, the paper clarifies necessary and sufficient conditions and bounds on code length and demonstrates code construction method of the optimal codes and evaluation of these codes from the perspectives of error correction/detection capability and decoder hardware complexity. Eiji Fujiwara, Tepparit Ritthongpitak, Masato Kitakami |
IEEE Trans. Computers | 3 |
| 1994 | A class of error-correcting codes for byte-organized memory systemsabstractError-locating codes (EL codes), first proposed by J.K. Wolf and B. Elspas in 1963, have the potential to be used to identify the faulty module for fault isolation and reconfiguration in fault-tolerant computer systems. This paper proposes a new class of EL codes suitable for memory systems organized with b-bit (b/spl ges/2) byte-organized semiconductor memory chips that are mounted on memory cards each having B-bit width. The proposed linear code, called the S/sub b/B/EL code, identifies erroneous memory card locations containing a faulty byte-organized chip. Another linear code proposed in this paper, the SEC-S/sub b/B/EL code, corrects single-bit errors induced by alpha particles and, for byte errors, it locates erroneous card positions containing a faulty chip. This paper describes design methods of the proposed codes and shows an evaluation of the decoding hardware and the error detection capabilities.> Eiji Fujiwara, Masato Kitakami |
IEEE Trans. Inf. Theory | 2 |