Paralfetchspeeds up application launches on personal computing/communication devices, by means of: 1) accurate collection of launch-related disk read requests, 2) pre-scheduling of these requests to improve I/O throughput during prefetching, and 3) overlapping application execution with disk prefetching for hiding disk access time from the execution of the application. We implementedParalfetchunder Linux kernels on a desktop/laptop PC, a Raspberry Pi 3 board, and an Android smartphone. Tests with popular applications show thatParalfetchsignificantly reduces application launch times on flash-based drives and hard disk drives, and it outperformsGSoC Prefetch[18] andFAST[21], which are representative application prefetchers available for Linux-based systems.

Multi-terabyte large memory systems are often characterized by more than two memory tiers with different latency and bandwidth. Multi-tiered large memory systems call for rethinking of memory profiling and migration because of the unique problems unseen in the traditional memory systems with smaller capacity and fewer tiers. We develop MTM, an application-transparent Multi-Tiered Memory management framework, based on three principles: (1) connecting the control of profiling overhead with the profiling mechanism for high-quality profiling; (2) building a universal page migration policy on the complex multi-tiered memory for high performance; and (3) introducing huge page awareness. We evaluate MTM using common big-data applications with realistic working sets (hundreds of GB to 1 TB). MTM outperforms seven solutions by up to 42% (17% on average).

Efficient use of caching space is crucial in block I/O caching schemes due to the high cost of caching media. This paper introduces EximCache, a novel scheme that prioritizes blocks not promptly managed by the OS readahead framework, addressing the performance criticality of block I/Os. Experimental results demonstrate that EximCache reduces caching space usage significantly while imposing minimal performance overhead during application launches and Linux boot.

NAND flash storage has become a standard choice in consumer electronics and is gaining popularity in enterprise systems due to its superior performance and low-power consumption. While its cost disadvantage is rapidly fading thanks to multibit cell technologies and 3-D stacking architectures, the challenge of limited endurance is still lingering and is expected to become more daunting as bits-per-cell continues to increase. In this article, we propose a novel flash translation layer (FTL) design named AxFTL (Approximate FTL) that extends the lifetime of NAND flash storage for error-tolerant applications. For error-tolerant data, AxFTL adopts shallow erase that lowers erase voltage to reduce the erase-induced wearing at the cost of an increased error rate. AxFTL manages multiple groups of blocks by error rates and allocates them according to the error tolerance of write requests. The key components of AxFTL include error tolerance-aware garbage collection and wear leveling schemes that manage the blocks with different error rates with minimal overhead. We implement AxFTL in an SSD simulator for the evaluation of the lifetime improvement and the actual allocation of the blocks. For application-level evaluation, we apply AxFTL to compressed video storage and evaluate the quality of video playback. Our experimental results show that AxFTL greatly improves the lifetime of NAND flash storage by 61% while maintaining a high structural similarity (SSIM) of 0.86 as compared to the conventional FTL.

By overlapping disk accesses with computation-intensive operations, prefetching can reduce delays in launching an application and in loading significant amounts of data while the application is running. The key to effective prefetching is making the tradeoff between the mining accuracy of selecting relevant blocks, and the time to decide those blocks. To address this problem, we propose a new prefetcher called ClusterFetch. In its learning mode, ClusterFetch detects periods of intensive disk accesses by monitoring the speed at which read requests are queued; it re-organizes these reads and locates the file opened by the application just before each such period. During subsequent runs of the same application, ClusterFetch prefetches the data associated with the opening of a “trigger” file. Our experimental results show that ClusterFetch implemented in Linux can reduce the application launch time by up to 41.3 percent and the loading time by up to 38.2 percent, while taking up less than 200 KB of main memory.

TrapFetch is trained by monitoring the read requests issued by an application. It detects bursts of disk reads, determines the appropriate addresses at which breakpoints should be inserted in the application and library codes prior to the bursts of reads, and then logs this information with the data requested during the interval between each consecutive pair of breakpoints. When the application and library codes are loaded from the disk into memory, TrapFetch inserts breakpoints at the designated addresses based on the logs. During subsequent runs, TrapFetch is invoked at each breakpoint when it prefetches the corresponding data into the page cache. This approach is effective during both launch and run-time. TrapFetch operates at the user level, thus avoiding interference with other applications. In experiments on five popular applications (FlightGear, SpeedDreams 2, Pillars of Eternity, Eclipse, and VegaStrike), TrapFetch reduced the time for launch by up to 39.7% and time for run-time data-loading by up to 63.7%.

Application loading times can be reduced by prefetching disk blocks into the buffer cache. Existing prefetching schemes for general workloads suffer from significant overheads and low accuracy. ClusterFetch is a lightweight prefetcher that identifies continuous sequences of I/O requests and identifies the files that trigger them. The next time that the same files are opened, the corresponding disk blocks are prefetched. In experiments, ClusterFetch reduced the launch time, by which we refer to the latency that first occurs when a program runs, by 15.2 to 30.9%, and loading times, meaning the delays that are incurred while additional data is loaded from the disk during program execution, by 15.9%.

Predictable and guaranteed response is an essential characteristic of safety-critical real-time systems. Thus we need to guarantee that the end-to-end latency of data exchange within such a system is always bounded and controlled, so that the overall system behavior is predictable and safe. In this paper, we propose a method for determining the worst-case delay when a packet traverses a network that consists of real-time crossbar switches. These switches guarantee that any feasible traffic can be switched in two clock periods by adopting an optimal clearance-time switching policy together with clock-driven scheduling. We also propose a switching architecture that introduces a delay buffer and virtual output queues to meet the one-shot traffic assumption required for optimal clearance-time switching. By removing the impractical assumptions made in previous works, we are able to derive a more accurate delay bound for real-world scenarios.

Application launch time is an important performance metric to user experience in desktop environment. The launch time mostly depends on the performance of secondary storage. There is a cost-performance trade-off in using hard disk drive (HDD) or solid-state drive (SSD). Thus, application launch times can be reduced by utilizing SSDs as caches for slow HDDs. We propose a new SSD caching scheme which migrates data blocks from HDDs to SSDs. Since our scheme operates entirely in the file system level and does not require an extra layer for mapping SSD-cached data, which is essential in most other schemes, our scheme does not incur mapping overheads that cause significant burdens on main memory, CPU, and SSD cache itself. Experimental results demonstrate our scheme yields 56% of performance gain in application launch.

Active storage devices further improve their performance by executing “intelligence functions,” such as prefetching and data deduplication, in addition to handling the usual I/O requests they receive. Significant research has been carried out to develop effective intelligence functions for the active storage devices. However, laborious and time-consuming efforts are usually required to set up a suitable experimental platform to evaluate each new intelligence function. Moreover, it is difficult to make such prototypes available to other researchers and users to gain valuable experience and feedback. To overcome these difficulties, we propose$\tt {IOLab}$, a virtual machine (VM)-based platform for evaluating intelligence functions of active storage devices. The VM-based structure of$\tt {IOLab}$enables the evaluation of new (and existing) intelligence functions for different types of OSes and active storage devices with little additional effort.$\tt {IOLab}$also supports real-time execution of intelligence functions, providing users opportunities to experience latest intelligence functions without waiting for their deployment in commercial products. Using a set of interesting case studies, we demonstrate the utility of$\tt {IOLab}$with negligible performance overhead except for the VM’s virtualization overhead.

Quality of service (QoS), and in particular reliability and low latency, are essential qualities of safety-critical wireless systems for medical applications. However, wireless links are typically prone to bursts of errors, with characteristics which vary over time. We propose a wireless system suitable for real-time remote patient monitoring in which both the necessary reliability and a bounded end-to-end delay are achieved by an efficient error control scheme. We have paired an example electrocardiography (ECG) application to this wireless system. We also developed a tool chain to assess various combinations of system parameters: we can determine the QoS in terms of the packet-delivery ratio and the end-to-end latency, and also the size of jitter buffer required for seamless ECG monitoring services. A realistic assessment, based on data from the MIT-BIT arrhythmia database, shows that the proposed wireless system can achieve an appropriate level of QoS for real-time ECG monitoring if link-level error control is appropriately implemented.

Quality of service (QoS) and, in particular, reliability and a bounded low latency are essential attributes of safety-critical wireless systems for medical applications. However, wireless links are typically prone to bursts of errors, with characteristics which vary over time.We propose a wireless system suitable for real-time remote patient monitoring in which the necessary reliability and guaranteed latency are both achieved by an efficient error control scheme. We have paired an example remote electrocardiography application to this wireless system. We also developed a tool chain that uses a formal description of the proposed wireless medical system architecture in the architecture analysis and design language to assess various combinations of system parameters: we can determine the QoS in terms of packet-delivery ratio and the service latency, and also the size of jitter buffer required for seamless ECG monitoring. A realistic assessment, based on data from the MIT-BIT arrhythmia database, shows that the proposed wireless system can achieve an appropriate level of QoS for real-time ECG monitoring if link-level error control is correctly implemented. Additionally, we present guidelines for the design of energy-efficient link-level error control, derived from energy data, obtained from simulations.

BCMCS (broadcast and multicast services) greatly increase the capacity of CDMA2000 mobile networks for multimedia broadcasting, but only require minor changes to existing radio and core network protocols. To provide high-quality multimedia services over error-prone wireless networks, we need to control delay, because it is one of the most important QoS parameters for multimedia applications. We identified error control using Reed-Solomon (RS) forward error correction (FEC) in the medium access control (MAC) layer as a significant cause of delay variation, and have proposed a novel analytic model that can predict the time required for RS decoding at a mobile, under different levels of block interleaving and for varying conditions of the Rayleigh fading channel at that mobile. This model enables us to estimate the buffer size required to ensure seamless multimedia services.

3GPP2 has recently introduced the Broadcast and Multicast Services (BCMCS) architecture for cdma2000 lxEV-DO wireless networks to enable service providers to broadcast multimedia content such as MPEG-4 video. For MAC-layer forward error correction the BCMCS scheme uses the Reed-Solomon (RS) decoding process, which consumes a considerable amount of energy on mobile phones. To address this problem, we first characterize the energy consumption of the decoder with respect to its components: the data decoder, error locator and erasure decoder. Based on this detailed energy characterization we propose an analytic energy model which takes account of different levels of bit error rate in the forward traffic channel. This model is then verified experimentally on an ARM microprocessor-based testbed. Our results will help design energy-efficient BCMCS systems for 3G cellular networks