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Yuan Taur

dblp:94/3139 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2001
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 89% Memory systems · 11%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
low-power circuit design		 0.022001
Device scaling limits of Si MOSFETs and their application dependencies · Proc. IEEE 2001
CMOS scaling into the nanometer regime · Proc. IEEE 1997
Integrated circuit design › semiconductor devices › device scaling
CMOS scaling limits		 0.012001
Device scaling limits of Si MOSFETs and their application dependencies · Proc. IEEE 2001
Integrated circuit design
digital circuit design		 0.012001
Device scaling limits of Si MOSFETs and their application dependencies · Proc. IEEE 2001
Integrated circuit design › emerging device technologies
alternative device structures		 0.011997
CMOS scaling into the nanometer regime · Proc. IEEE 1997
Integrated circuit design › technology scaling
CMOS scaling		 0.011997
CMOS scaling into the nanometer regime · Proc. IEEE 1997
Integrated circuit design › semiconductor devices
short-channel effects		 0.011997
CMOS scaling into the nanometer regime · Proc. IEEE 1997
Memory systems
DRAM		 0.012001
Device scaling limits of Si MOSFETs and their application dependencies · Proc. IEEE 2001
Memory systems › random-access memory
SRAM		 0.012001
Device scaling limits of Si MOSFETs and their application dependencies · Proc. IEEE 2001

Methods — techniques the papers use, named apart from their topics

device physics modeling · 0.0
YearPublicationVenuePosition
2001 Device scaling limits of Si MOSFETs and their application dependencies
abstract
This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
David J. Frank, Robert H. Dennard, Edward J. Nowak, Paul M. Solomon, Yuan Taur, H.-S. Philip Wong
 Proc. IEEE5
1997 CMOS scaling into the nanometer regime
abstract
Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.
Yuan Taur, Douglas A. Buchanan, David J. Frank, Khalid E. Ismail, Shih-Hsien Lo, George A. Sai-Halasz, Raman G. Viswanathan, Hsing-Jen C. Wann, Shalom J. Wind, H.-S. Philip Wong
 Proc. IEEE1