This paper presents a systematic methodology for exploring possible processor arrays of scalable radix 4 modular Montgomery multiplication algorithm. In this methodology, the algorithm is first expressed as a regular iterative expression, then the algorithm data dependence graph and a suitable affine scheduling function are obtained. Four possible processor arrays are obtained and analyzed in terms of speed, area, and power consumption. To reduce power consumption, we applied low power techniques for reducing the glitches and the Expected Switching Activity (ESA) of high fan-out signals in our processor array architectures. The resulting processor arrays are compared to other efficient ones in terms of area, speed, and power consumption.

Implantable cardioverter defibrillators (ICDs) detect and treat dangerous cardiac arrhythmia. This paper describes a low-power VLSI neural network chip which acts as an intracardiac tachycardia classification system. A robust neural network reduces the impact of noise, drift and offsets that are inherent in analog applications. Our system uses a Kohonen self-organizing map, and has a typical power consumption of a few milliwatts.