Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose processors and ASICs alike. One way architects have bridged the performance gap between FPGAs and ASICs is through the inclusion of specialized components such as multipliers, RAM modules, and microcontrollers. Another dedicated structure that has become standard in reconfigurable fabrics is the arithmetic carry chain. Currently, it is only used to map arithmetic operations as identified by HDL macros. For non-arithmetic operations, it is an idle but potentially powerful resource

Reconfigurable fabrics cater to a wide variety of applications, but have adopted specialized components to allow efficient implementation of performance-critical arithmetic operations. Carry chains have been integrated into the fabric typically as an optimized ripple-carry chain. However, in non-arithmetic operations the carry chain goes unused, when it could be a valuable adjacent-cell interconnect resource. This paper presents a cell architecture facilitating reuse, as well as an analysis of the potential benefits of reuse for an sampling of common of algorithms using commercial FPGAs. Technology map experiments indicate that a variety of applications can benefit from reuse, with utilized routing resources reduced by up to 13% and maximum clock frequency increased by up to 47%.

Ripple-carry architectures are the norm in today's reconfigurable fabrics. They are simple, require minimal routing, and are easily formed across arbitrary cells in a fabric. However, their computation delay grows linearly with operand width. Many different fabric carry-chains have been presented in literature offering non-linear delays, but generally require a significant investment in routing and processing area. Carry-skip chains are well-known in arithmetic logic design, and although they too possess a linear delay, their performance is 2times or more faster than simple ripple-carry schemes. They require an expanded carry chain and minimal extra logic, but offer impressive speed-ups for arithmetic. This paper presents a reconfigurable cell that supports carry-skip arithmetic using a multi-bit carry chain achieving 2 middot k middot b+ n/b performance, where b is the block size and k is an architecture constant. The cell is specialized for arithmetic and Boolean operations with reduced configuration memory. Additional resources are provided to reuse the multi-bit carry chain for 3-source operand arithmetic to explore how multi-bit chains can be reused

The Radon transform (RT) is a widely studied algorithm used to perform image pattern extraction in fields such as computer graphics, medical imagery, and avionics. Real time implementation of the discrete RT (DRT) is extremely difficult due to its use of complex trigonometric functions and O(N/sup 3/) time complexity, making its use in video applications difficult. A O(N/sup 2/lgN) approximate discrete (ADRT) has been presented in literature (Brady, 1998) that allows highly parallel computation. This paper presents an architecture that uses the ADRT to create a computation architecture known as the xADRT. Performance analysis indicates that it can achieve a refresh rate of 10 frames per second for use in real time image processing applications.

Double link failure models, in which any two links in the network fail in an arbitrary order, are becoming critical in survivable optical network design. A significant finding is that designs offering complete dual-failure restorability require almost triple the amount of spare capacity. In this paper, networks are designed to achieve 100% restorability under single link failures, while maximizing coverage against any second link failure in the network. In the event of a single link failure, the restoration model attempts to dynamically find a second alternate link-disjoint end-to-end path to provide coverage against a sequential overlapping link failure. Sub-graph routing (M. T. Frederick et al., Feb. 2003) is extended to provide dual-failure restorability for a network provisioned to tolerate all single-link failures. This strategy is compared with shared-mesh protection. The results indicate that sub-graph routing can achieve overlapping second link failure restorability for 95-99% of connections. It is also observed that sub-graph routing can inherently provide complete dual-failure coverage for ~72-81% of the connections