The effect of CVD-SiO/sub 2/ films on the reliability of GaAs MESFET with Ti/Pt/Au gate metal was investigated. It was found that the mean time to failure (MTTF) of MESFET with 350/spl deg/C-depositied SiO/sub 2/ was only about one-seventh of that of the ones with 440/spl deg/C-SiO/sub 2/. It was also found that, in the storage test at 300/spl deg/C for 24 hours, diffusion of Pt into GaAs was accelerated when the SiO/sub 2/ deposition temperature was lower than 380/spl deg/C. FT-IR spectra indicated that the lower deposition temperature leads to a higher concentration of the residual hydrogen in SiO/sub 2/. Thermal differential spectrometry (TDS) demonstrated that hydrogen in SiO/sub 2/ could migrate even below 300/spl deg/C. In conclusion, the residual hydrogen in SiO/sub 2/ causes the degradation phenomena.

A high-speed two-dimensional (2-D) topography simulator which operates in X-Windows has been developed. This program, named TIGER (Topography Image GEneration Routine), uses a newly developed pixel model, in which regions of the same material are depicted by pixels with the same value (i.e. the same color) and material boundaries are regarded as color boundaries. New cross-sectional profiles are sequentially created by drawing basic geometrical figures on a cross-sectional profile of a former process step. No complex operations are required for boundary line definition, such as loop removal. Realistic cross sections of an LSI with three interconnection layers and an SST transistor with a complex structure were created by this simulator. The total simulation time is only one or two minutes for all the processing steps of an LSI.