In the semiconductor landscape, safeguarding integrated circuits against Hardware Trojans (HT) is critical.To address this pressing concern, supervised machine learning (ML) has emerged as a promising defense mechanism for HT detection. However, the vulnerability of supervised ML-based defense mechanisms to adversarial attacks poses a substantial challenge, potentially compromising model prediction performance. This paper presents a label flipping poisoning attack, strategically targeting supervised ML-based HT detection systems during the pre-silicon IC design phase. Leveraging the power of the Isolation Forest, our method first identifies potential Trojan nets through a process of random partitioning, flips their labels, and perturbs the model training process. Further, random subsampling is applied to select a subset of Trojan-free samples, whose labels are also flipped. This model-independent, untargeted, and black-box attack is evaluated against Trust-Hub & DeTrust Benchmarks, resulting in a substantial reduction in model recall, challenging the reliability of ML-based HT detection systems.

Approximate computing is an emerging computing technique for designing energy- and resource-efficient arithmetic circuits for error-resilient applications. Square root (SQR) computation is a fundamental and complex operation in various signal/image processing tasks. It demands high resource and energy consumption, making the square-rooter a crucial design element. This brief proposes a low-complexity logarithmic-based energy-efficient approximate square rooter (LESQ) for computing integer SQR using simple addition and shift operations. A partial error compensation scheme is also suggested for improved accuracy. The proposed approximate square rooter also enables various accuracy configurable modes to tradeoff error with hardware efficiency for targeted application requirements. LESQ achieves energy- and area-delay savings of up to 80% and 60%, respectively, compared to an accurate array-based square-rooter design. The proposed approximate design is tested on error-tolerant applications, such as image processing and amplitude modulation (AM) communication system.

This paper provides a detailed performance analysis of low power and high speed Look up Table (LUT) by using a circuit technique. Proper sizing of all the sleep transistors are done in the LUT to achieve an optimum power -delay relationship so that it can be used for fast growing low power applications. Also, we have implemented a benchmark circuit (8 × 10) encoder in Virtex-4, 90nm FPGA. As compared to the traditional 4-input LUT design, proposed design saves 12.8% of average power in high speed mode and 56.7% in low power mode with a little compromise in its speed.

This paper presents a new method to remove noise and enhance the image with the help of partial unsharp masking and conservative smoothing. In this method, unsharp masking is applied in partial way for detection of the edges and boundary lines in the image and then a conservative smoothing operation is applied on the selected areas to remove undesirable edges which represents the salt and pepper noise. Finally, the noise free edge image is added with the smoothed image to get the original image with reduced noise. The proposed method is compared with that of performance of mean and median filtering. The experimental results on synthetic and real images show the effectiveness of the proposed method.