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William J. Stenzel

dblp:94/4197 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1977
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design
arithmetic circuit design
0.011977
A Compact High-Speed Parallel Multiplication Scheme · IEEE Trans. Computers 1977
Integrated circuit design
digital circuit design
0.011977
A Compact High-Speed Parallel Multiplication Scheme · IEEE Trans. Computers 1977
Integrated circuit design › digital circuit design › arithmetic circuit design
multiplier design
0.011977
A Compact High-Speed Parallel Multiplication Scheme · IEEE Trans. Computers 1977
Integrated circuit design › digital circuit design › arithmetic circuit design
parallel multiplier
0.011977
A Compact High-Speed Parallel Multiplication Scheme · IEEE Trans. Computers 1977

Methods — techniques the papers use, named apart from their topics

partitioning algorithm · 0.0
YearPublicationVenuePosition
1977 A Compact High-Speed Parallel Multiplication Scheme
abstract
This paper discusses a compact, fast, parallel multiplication scheme of the generation-reduction type using generalized Dadda-type pseudoadders for reduction and m X m multipliers for generation. The implications of present and future LSI are considered, a partitioning algorithm is presented, and the results obtained for a 24 X 24-bit implementation are discussed.
William J. Stenzel, William J. Kubitz, Gilles H. Garcia
IEEE Trans. Computers1