The backhaul networks for the 5G networks consist of different links that handle massive heterogeneous traffic. Fulfilling the QoS requirement of users to comply with the growth and increasing revenue is a challenge for the service providers. We address QoS parameters like bandwidth and delay for the user’s transport network. We use Software-Defined Networking and solve this problem. We have added a component Flowlet based Multiple Constraint Optimal Paths (MCOP) for packet forwarding by taking input as QoS requirements and creating a logical network in backhaul transport networks when needed for the elephant traffic. Due to security reasons, the transport network cannot access L7 to identify the application type. We have added an application identification component to detect the traffic type. We use an experimental platform using mininet and OpenFlow. Our proposed algorithm has higher QoS performance than the conventional method after the primary link exhaust capacity. It takes around 20 to 30 packets to learn the traffic type up to L6 parameters. Our approach identifies 73.10% of traffic type. The multipath usage helps improve revenue growth by assuring the dynamic allocation of the resources to the customer for elephant flow with the required QoS.

Processing-in-memory (PIM) chips that integrate processor logic into memory devices offer a new opportunity for bridging the growing gap between processor and memory speeds, especially for applications with high memory-bandwidth requirements.The Data-IntensiVe Architecture (DIVA) system combines PIM memories with one or more external host processors and a PIM-to-PIM interconnect.DIVA increases memory bandwidth through two mechanisms: (1) performing selected computation in memory, reducing the quantity of data transferred across the processor-memory interface; and (2) providing communication mechanisms called parcels for moving both data and computation throughout memory, further bypassing the processor-memory bus.DIVA uniquely supports acceleration of important irregular applications, including sparse-matrix and pointer-based computations.In this paper, we focus on several aspects of DIVA designed to effectively support such computations at very high performance levels: (1) the memory model and parcel definitions; (2) the PIM-to-PIM interconnect; and, (3) requirements for the processor-to-memory interface.We demonstrate the potential of PIMbased architectures in accelerating the performance of three irregular computations, sparse conjugate gradient, a natural-join database operation and an object-oriented database query.

In this paper we describe the design and implementation of a 190-MHz pipelined 4-Kbyte instruction and data cache. The caches are designed in 1.0-µm CMOS and measure 0.78 x 0.47 cm 2 . This paper describes the microarchitecture, cache timing, circuit implementation, and layout of both the instruction and the data cache. The key features of these caches are pipelined execution and the use of dynamic single-phase clock logic. We discuss the interface of this cache with the processor core and the off-chip controller. This paper also describes the pipelined structure of the cache and the miss detection and handling logic. Published in ISCAS `95, Seattle 1 ABSTRACT In this paper we describe the design and implementation of a 190-MHz pipelined 4-Kbyte instruction and data cache. The caches are designed in 1.0-µm CMOS and measure 0.78 x 0.47 cm 2 . This paper describes the microarchitecture, cache timing, circuit implementation, and layout of both the instruction and the data cache. T...

Clocked (synchronous) and self-timed (asynchronous) methodologies represent the two principal design approaches associated with timing control and synchronization of digital systems. In the paper, clocked and asynchronous instruction pipelines are modeled and compared. The approach which yields the best performance is dependent on technology parameters, operating range and pipeline algorithm characteristics. Design curves are presented which permit selection of the best approach for a given application and technology environment.>