Memristive technologies can enable novel mixed-mode (MM) circuit architectures, where diverse stateful and non-stateful logic operations are executed by the same physical device. Recently introduced optimal synthesis procedures for MM circuits have achieved 3-5X area and latency improvements compared with single-mode memristive logic families, yet such methods are not scalable. In this paper, we present a synthesis approach for MM circuits that leverages synthesis techniques for majority-inverter graphs (MIGs). MIG vertices are natural descriptions of non-stateful voltage-input (V-op) and stateful resistance-input (R-op) logic operations. Our synthesis can handle circuits with up to 27 inputs and achieves an average reduction of 80% in required devices and 65% delay when compared to a state-of-the-art approach for R-ops.

Analog compute-in-memory (ACIM) architectures emerged as energy efficient matrix–vector multiplication accelerators utilized for neural network inference in power-constrained environments. However, the security implications of ACIM hard-ware remain almost entirely unexplored. In particular, no previous work has evaluated information leakage of fabricated ACIM hardware through power side-channels. This work presents the first measured power side-channel analysis of a fabricated 28 nm ACIM macro. Using a convolutional neural network (CNN) work-load, we show that power traces exhibit strong data-dependent information leakage that allows accurate reconstruction of private input images, with a mean structural similarity index measure (MSSIM) of up to 0.71.

System-Level Test (SLT) is important in semiconductor testing as it can detect defects missed by traditional methods. Test engineers use off-the-shelf software to manually compose test suites, often written in high-level languages such as $\mathrm{C} / \mathrm{C}++$ or Rust. Several methods for automatically generating test programs have been investigated, using assembly language. However, one could argue that the resulting test programs are not capturing all possible interactions in actual software. Large Language Models (LLMs) can generate code in high-level languages closer to actual software. In this work, we examine the limitations of LLMs and high-level languages for generating SLT programs. We run an experiment using genetic programming (GP) to find an assembly snippet with the highest power consumption. Then, we utilize LLMs to generate $\mathbf{C}$ code and demonstrate that the compiler, the enabled optimization level, and the LLM have a significant influence on the resulting power consumption. Furthermore, we show via decompilation that the snippet from the GP run has no direct equivalent in C. Finally, we demonstrate that the initial values have a significant impact on power consumption for both the GP-generated and the decompiled snippet.

Stochastic computing offers low-power and compact arithmetic for neural network inference, but achieving fault tolerance typically requires long bitstreams that create latency bottlenecks for real-time applications. This work introduces an adaptive-precision framework for fault-tolerant stochastic long short-term memory (SLSTM) networks that dynamically assigns stochastic number lengths based on computational criticality. The proposed Cell-based Gradient Sensitivity Search (CGSS) algorithm identifies the most faultsensitive LSTM cells through gradient-based analysis, enabling targeted allocation of longer bitstreams to critical computations while using shorter, low-latency bitstreams for less sensitive operations. The proposed adaptive-precision SLSTM accelerator validates our approach by achieving up to $3.4 \times$ latency reduction, 40% area savings, and 58% power reduction while maintaining fault tolerance equivalent to fixed highprecision SLSTM designs under higher fault rates. These results demonstrate that criticality-guided adaptive-precision is important for making fault-tolerant stochastic neural networks practically viable in resource-constrained environments.

Memristive crossbars are attractive for in-memory computing due to their integration density combined with compute and storage capabilities of their basic devices. However, yield and fidelity of emerging memristive technologies can make their reliable operation unattainable, thus raising interest in simpler topologies. In this paper, we consider synthesis of Boolean functions on 1D memristive line arrays. We propose an optimal procedure that can fully utilize the rich electrical behavior of memristive devices, mixing stateful (resistance-input) and non-stateful (voltage-input) operations as desired by the designer, leveraging their respective strengths. The synthesis method is based on Boolean satisfiability (SAT) solving and supports flexible constraints to enforce, e.g., restrictions of the available peripher-als. We experimentally validate memristive logic circuits beyond individual logic gates by demonstrating the operation of a Galois field multiplier using a 1D line array of 10 memristors in parallel, highlighting the robust performance of our proposed mixed-mode circuit and its synthesis procedure.

The continuous wavelet transform (CWT) is essential for analyzing non-stationary signals in edge computing, but traditional implementations are limited by high power demands, particularly in resource-constrained environments. Stochastic computing (SC), which leverages probabilistic bit-streams and compact arithmetic units, provides a promising alternative for ultra-low-power CWT designs. However, such circuits are vulnerable to transient faults and involve careful power-reliability trade-offs. This work presents the first SC-based CWT hardware design aimed at applications with severe resource constraints, including power consumption, accuracy, and fault tolerance. We comprehensively analyzed our design, which features a Sobol-based pseudo-random number source and accumulative parallel counter-based addition. In a fault-free environment, this design achieves an 84% power reduction over non-SC CWTs and a 37% reduction over other SC designs. It also achieves up to 64% area savings and reduces latency by 8×. Under a 30% fault rate, our design improves RMSE by 74% over binary CWTs and 32% over other SC implementations.

Process capability index is a useful metric for maintaining the quality of semiconductor manufacturing. We address, for the first time, the influence of Automated Test Equipment (ATE) drift on process capability. An integrated approach for interpretation of process capability indices considers not only the part variation associated with device manufacturing process, but also the measurement variation due to wearing calibration of the ATE. With a polynomial regression model of ATE correction data and Device Under Test (DUT) measurement results we account for measurement variation due to ATE drift and understand how it influences process capability studies.

Human activity recognition (HAR) is a challenging area of research with widespread applications in human-computer interaction. Recent advances in neural networks (NNs) have greatly improved the methods of HAR feature extraction from wearable sensor data and increased the interest in their classification using NNs. While most prior work has relied on software implementations of NN-based HAR, we investigate for the first time hardware implementations for use in resource-constrained edge devices. Emerging edge and near-sensor systems must avoid costly communication with the cloud and perform complex classification tasks locally. This points to using low-area hardware technology such as stochastic computing (SC) and enhanced feature extraction methods such as wavelet transform (WT). We explore the wavelet-assisted stochastic-enabled neural network (WASENN) design for HAR. The NN types we consider are convolutional neural networks and long short-term memory networks. We study both partial and full versions of WASENN and evaluate their performance and resource utilization on the UCI HAR and WISDM datasets. Our hardware synthesis results show the superiority of the wavelet transform in accuracy and size. They also show that SC reduces area and power by 32% and 74% respectively with little impact on classification accuracy.

Marginal defects, such as high-resistance short or low-resistance open defects, are hard to detect by conventional pass-fail test methods because their manifestations are practically indistinguishable from the effects of regular variations. However, their coverage is essential for circuits with high-quality requirements and/or when early-life failures are a concern. In this paper, we propose an alternative detection concept based on evaluating several parametric responses of a circuit against a machine learning (ML) model. We use a 14nm FinFET transistor model validated against industrial measurements. We show that high detection performance is possible even when unsupervised learning that does not consider defective behavior is used; to this end, the procedure is generic. Moreover, an AUC score of over 0.96 is achieved when only measurements from a single voltage level are utilized, in contrast to earlier work. We also present a procedure to select a reduced set of test sequences, achieving an improvement of 50% reduction with a limited impact on detection performance.

Stochastic computing (SC) provides low-area, power-efficient hardware solutions suitable for edge systems, but its scalability poses challenges due to its precision limitations, especially in noisy environments. This paper investigates the fault tolerance of key SC components, such as stochastic number generators (SNGs) and activation functions (AFs), within recurrent and sequential networks like long short-term memory (LSTM) networks. We inject bit-flip faults into a network’s most sensitive inputs, weights and AFs, and study fault propagation across different network layers. Our findings reveal that SC component choices significantly influence fault tolerance. For example, networks using Sobol-based SNGs with tanh AFs exhibited stronger resilience than those with LFSR-based SNGs and ReLU AFs, by maintaining higher accuracy under fault conditions. However, the accuracy of the networks declined significantly under simultaneous faults in inputs, weights and AFs. Additionally, while increasing stochastic number lengths improved fault tolerance, they also increased latency. Nevertheless, the SC networks achieved up to 54% area and 72% power savings, making them ideal for resource-constrained applications. We also found that there is a trade-off between efficiency and fault tolerance: SC designs that focus on resource efficiency may struggle in noisy environments, where fault-tolerant SC designs are more effective. This implies that fault resilience in SC architectures depend heavily on design choices and cannot be assumed inherent across all configurations.

Recent advances in near-sensor computing have prompted the need to design low-cost digital filters for edge devices. Stochastic computing (SC), leveraging its probabilistic bit-streams, has emerged as a compelling alternative to traditional deterministic computing for filter design. This paper examines error tolerance, area and power efficiency, and accuracy loss in SC-based digital filters. Specifically, we investigate the impact of various stochastic number generators and increased filter complexity on both FIR and IIR filters. Our results indicate that in an error-free environment, SC exhibits a 49% area advantage and a 64% power efficiency improvement, albeit with a slight loss of accuracy, compared to traditional binary implementations. Furthermore, when the input bit-streams are subject to a 2% bit-flip error rate, SC FIR and SC IIR filters have a much smaller performance degradation (1.3X and 1.9X, respectively) than comparable binary filters. In summary, this work provides useful insights into the advantages of stochastic computing in digital filter design, showcasing its robust error resilience, significant area and power efficiency gains, and trade-offs in accuracy compared to traditional binary approaches.

The rising complexity of integrated devices has led to new defect types and failure modes at the system level that are not detected by structural tests. System-Level Test (SLT) is another test step to combat this challenge. SLT is in charge of exercising system-level interactions between hardware components and software. Non-functional properties, e.g., temperature, play a major role in SLT.This work focuses on the automatic generation of assembly test programs for SLT that aim to indirectly maximize a particular non-functional property, for example, the temperature. It is based on two-step generation with genetic algorithms. First, a fast architectural simulation is used with the genetic algorithm to provide a structure for the test programs. Afterward, an additional generation is done on the hardware to optimize the initial register contents of the program.The case study for gathering experimental results is a super-scalar out-of-order RISC-V processor, the Berkeley Out-of-Order Machine (BOOM). Experimental results show that the two-step generation is more effective in converging to a better power-hungry test program than only using the power consumption as a fitness function for the genetic algorithm.

System-Level Test (SLT) has been an integral part of integrated circuit test flows for over a decade and continues to be significant. Nevertheless, there is a lack of systematic approaches for generating test programs, specifically focusing on the non-functional aspects of the Device under Test (DUT). Currently, test engineers manually create test suites using commercially available software to simulate the end-user environment of the DUT. This process is challenging and laborious and does not assure adequate control over non-functional properties. This paper proposes to use Large Language Models (LLMs) for SLT program generation. We use a pre-trained LLM and fine-tune it to generate test programs that optimize non-functional properties of the DUT, e.g., instructions per cycle. Therefore, we use Gem5, a microarchitectural simulator, in conjunction with Reinforcement Learning-based training. Finally, we write a prompt to generate C code snippets that maximize the instructions per cycle of the given architecture. In addition, we apply hyperparameter optimization to achieve the best possible results in inference.

Side-channel attacks represent a significant and persistent threat to hardware security. One effective strategy for safeguarding hardware components against these attacks involves the implementation of masking schemes. Among these schemes, Inner Product Masking (IPM) has received considerable attention and analysis in prior research. Inner Product Masking with Error Detection aims to extend the security provided by IPM to Fault-Injection attacks. This can be achieved by incorporating (linear) repetition code for fault detection (IPM-FD) or by integrating a non-linear robust error detection into the scheme (IPM-RED). IPM-RED can detect (with non-zero probability) every fault regardless the number of bits it flips. However, this robustness comes with a cost, a non-linear function may leak via the physical channels more information than a linear one. This paper shows that information leakage from IPM-RED is marginal. An improved IPM-RED masking scheme is also presented, and an empirical side-channel leakage analysis of the protected Advanced Encryption Standard (AES) design utilizing the Test Vector Leakage Assessment (TVLA).

Test application to state-of-the-art integrated circuits usually consists of multiple test insertions: wafer sort, final test and system-level test (SLT). This paper considers optimization of test content, taking requirements of specific scenarios, such as expected yield levels, test costs and criticality of test escapes, into account. An integrated cost model is proposed and applied to four different test setups on a medium-complexity RISC-V microprocessor. Our results indicate opportunities for up to ~ 40% total cost reduction compared to today’s industrial practice. They also provide insights on the relative importance of various cost contributors, such as the number of available scan test insertions or the specific SLT workload used.

Quick progress in memristive technologies has led to their consideration for several potential applications, many of which are security-critical. New possibilities of memristors, including their unique combination of non-volatile storage and compute capabilities, make them particularly attractive to edge applications, which are physically exposed to their users and therefore to potential attackers. Therefore, practical deployment of memristive circuitry for, e.g., cryptographic (sub-)modules or on-chip neural network inference, is only feasible when their vulnerability to physical attacks is understood and addressed. We evaluate experimentally one relevant class of physical attacks, namely side-channel attacks, under varying external conditions, namely temperature and magnetic fields. Using a small cryptographic construction, we evaluate both white-box and black-box attack varieties, using respective cryptanalytic techniques. Our results show that, while non-nominal conditions can complicate attacks, the information leakage remains and the secrets are extractable with additional knowledge about the memristive devices. This suggests the need to consider possible external disturbances during security evaluation.

The security of computer systems can be increased effectively by using cryptographic co-processors to encapsulate secrets and speed-up the computationally intensive cryptographic functions. This can be especially advantageous for Internet of Things devices, as they usually have to be very efficient in cost, space and timing. However, these devices are also at greater risk of becoming targets of hardware attacks, as they handle sensitive data and are physically exposed to a nearly unrestricted population of users. This paper describes a modular cryptographic co-processor, allowing it to be applied in different scenarios and easily adjusted to concrete system specifications. The co-processor design is also open-source and freely available for anyone to further applications and modifications. It implements the basic cryptographic functions of symmetric encryption, hashing and a pseudo random number generation, with an interface to a true random number generator. In addition, the co-processor offers additional interfaces for key generation. A specific realization is presented in detail, compared to existing solutions, and its resilience against various attacks is discussed.

With the continued success of the open RISC-V architecture, practical deployment of RISC-V processors necessitates an in-depth consideration of their testability, safety and security aspects. This survey provides an overview of recent developments in this quickly-evolving field. We start with discussing the application of state-of-the-art functional and system-level test solutions to RISC-V processors. Then, we discuss the use of RISC-V processors for safety-related applications; to this end, we outline the essential techniques necessary to obtain safety both in the functional and in the timing domain and review recent processor designs with safety features. Finally, we survey the different aspects of security with respect to RISC-V implementations and discuss the relationship between cryptographic protocols and primitives on the one hand and the RISC-V processor architecture and hardware implementation on the other. We also comment on the role of a RISC-V processor for system security and its resilience against side-channel attacks.

Approximate computing (AxC) has emerged as an attractive architectural paradigm especially for artificial-intelligence applications, yet its security implications are being neglected. We demonstrate a novel covert channel where the malicious sender modulates transmission by switching between regular and AxC realizations of the same computational task. The malicious receiver identifies the transmitted information by either reading out the workload statistics or by creating controlled congestion. We demonstrate the channel on both an Android simulator and an actual smartphone and systematically study measures to increase its robustness. The achievable transmission rates are comparable with earlier covert channels based on power consumption, but the malicious behavior of our channel is more stealthy and less detectable.

System-Level Test (SLT) emerged as an additional test step to detect manufacturing defects not caught by traditional testing. For SLT, the Device Under Test (DUT) is embedded into an environment that emulates the end-user application as closely as possible and runs workloads composed of existing off-the-shelf software. We present an automatic greybox SLT program generation method to find code snippets that control the DUT’s extra-functional properties, to achieve better characterization, or to improve the coverage of emerging defect types. In contrast to ATPG or formal methods, our method does not require structural information and relies solely on simulation results or hardware measurements to guide the generation. We show that our method outperforms hand-crafted snippets on a RISC-V super-scalar processor and look into possible reasons why the snippets perform the way they do.

The overwhelmingly widespread use of Internet of Things (IoT) in different application domains brought not only benefits, but, alas, security concerns as a result of the increased attack surface and vectors. One of the most critical mechanisms in IoT infrastructure is key management. This paper reflects on the problems and challenges of existing key management systems, starting with the discussion of a recent real-world attack. We identify and elaborate on the drawbacks of security primitives based purely on physical variations and - after highlighting the problems of such systems - continue on to deduce an effective and cost-efficient key management solution for IoT systems extending the symbiotic security approach in a previous work. The symbiotic architecture combines software, firmware, and hardware resources for secure IoT while avoiding the traditional scheme of static key storage and generating entropy for key material on-the-fly via a combination of a Physical Unclonable Function (PUF) and pseudo-random bits pre-populated in firmware.

Memristive technologies offer fascinating opportunities for unconventional computing architectures and emerging applications. While memristive devices have received substantial attention as sources of entropy for security applications, security vulnerabilities of memristive technologies for implementing cryptographic circuits have been largely neglected so far. In this article, we provide the first in-depth analysis of power side-channel analysis against memristive cryptographic implementations based on both: physical experiments and simulations. We show that power consumption models developed for CMOS are not fully adequate for memristive circuits. In particular, the memory effect makes even input-independent initialization cycles vulnerable to attacks that would be fundamentally impossible in CMOS technologies. We propose a memristive-oriented Power Estimation Model (mPEM) integrated into the Stochastic Approach (StA) framework and demonstrate its effectiveness against larger-scale circuits. Finally, we demonstrate that attack countermeasures that were effective for CMOS fail for fundamental reasons in the memristive case.

Test methods that can keep up with the ongoing increase in complexity of semiconductor products and their underlying technologies are an essential prerequisite for maintaining quality and safety of our daily lives and for continued success of our economies and societies. There is a huge potential how test methods can benefit from recent breakthroughs in domains such as artificial intelligence, data analytics, virtual/augmented reality, and security. The Graduate School on “Intelligent Methods for Semiconductor Test and Reliability” (GS-IMTR) at the University of Stuttgart is a large-scale, radically interdisciplinary effort to address the scientific-technological challenges in this domain. It is funded by Advantest, one of the world leaders in automatic test equipment. In this paper, we describe the overall philosophy of the Graduate School and the specific scientific questions targeted by its ten projects.

For emerging edge and near-sensor systems to perform hard classification tasks locally, they must avoid costly communication with the cloud. This requires the use of compact classifiers such as recurrent neural networks of the long short term memory (LSTM) type, as well as a low-area hardware technology such as stochastic computing (SC). We study the benefits and costs of applying SC to LSTM design. We consider a design space spanned by fully binary (non-stochastic), fully stochastic, and several hybrid (mixed) LSTM architectures, and design and simulate examples of each. Using standard classification benchmarks, we show that area and power can be reduced up to 47% and 86% respectively with little or no impact on classification accuracy. We demonstrate that fully stochastic LSTMs can deliver acceptable accuracy despite accumulated errors. Our results also suggest that ReLU is preferable to tanh as an activation function in stochastic LSTMs

Recent breakthroughs in machine learning (ML) technology are shifting the boundaries of what is technologically possible in several areas of Computer Science and Engineering. This paper discusses ML in the context of test-related activities, including fault diagnosis, post-silicon validation and yield optimization. ML is by now an established scientific discipline, and a large number of successful ML techniques have been developed over the years. This paper focuses on how to adapt ML approaches that were originally developed with other applications in mind to test-related problems. We consider two specific applications of learning in more depth: delay fault diagnosis in three-dimensional integrated circuits and tuning performed during post-silicon validation. Moreover, we examine the emerging concept of brain-inspired hyperdimensional computing (HDC) and its potential for addressing test and reliability questions. Finally, we show how to integrate ML into actual industrial test and yield-optimization flows.

Stochastic computing (SC) with its stream-based, probabilistic number representation promises large area and power benefits as well as increased error tolerance compared to conventional binary computing. While SC is less precise, it is considered a promising option for implementing neural network inferencing in ultra-low-power edge devices. SC-based Neural Networks (SCNNs) typically combine stochastic and binary components for interfacing and to alleviate certain SC limitations. Moreover, ultra-low-power VLSI for edge computing is often less reliable due to noisy environments or deliberate power-reliability trade-offs. In this work, we present the first detailed investigation of the behavior of an SCNN and its individual components on hardware prone to timing errors. Our results show that robustness of SC is highly dependent on specific design choices and that biases in the error distributions may even cause SCNNs to perform worse under certain circumstances than comparable binary implementations. It shows that robustness should be treated as a design goal in SC rather than taken for granted.

Identification of DeepFake video content is a challenging scientific problem that addresses a growing societal concern. We investigate the relationship between DeepFake detection by humans and by automatic methods based on state-of-the-art deep learning algorithms. The main novelty of our work is the consideration of videos that are transmitted through noisy channels and arrive with distortions. This reflects many practical environments, including surveillance based on cameras connected via noisy wireless links and videoconferencing in driving vehicles. We conduct a user study with 192 probands who classify real (genuine) and DeepFake videos with and without various classes of distortions. We find that today's deep neural networks (DNNs) outperform humans by far, whereas humans are heavily distracted by random noise from the channel. Moreover, DNNs are robust under distortions, achieving perfect classification on distorted data even when trained on distortion-free content. It appears that the human visual system and DNNs are approaching the DeepFake classification problem quite differently and their respective strengths and weaknesses are largely uncorrelated.

Human activity recognition (HAR) is a challenging area of research with many applications in human-computer interaction. With advances in artificial neural networks (ANNs), methods of HAR feature extraction from wearable sensor data have greatly improved and have increased interest in their classification using ANNs. Most prior work has only investigated the software implementations of ANN-based HAR. Here, we investigate, for the first time, two novel hardware implementations for use in resource-constrained edge devices. Through architecture exploration, we identify first a hybrid ANN we call DCLSTM incorporating the convolutional and long-short-term memory techniques. The second is a much more compact implementation WCLSTM that uses wavelet transforms (WTs) to enhance feature extraction; it can achieve even better accuracy while being smaller and simpler; it is therefore the better choice for resource-constrained applications. We present hardware implementations of these ANNs and evaluate their performance and resource utilization on the UCI HAR and WISDM datasets. Synthesis results on an FPGA platform show the superiority of the WT-assisted version in accuracy and size. Moreover, our networks achieve a better accuracy than earlier published works.

It has been previously shown that hardware implementation of fault attack countermeasures based on error-detecting codes (EDCs) can make the circuit more vulnerable to power analysis attacks. We revisit this finding and show that the hypothesis space can grow significantly when a state-of-the-art security-oriented robust EDC is properly crafted. We use the Roth-Karp decomposition as an analytical tool to prove that by a simple re-ordering of the EDC's bits, the number of extra bits needed to formulate the hypotheses becomes so large that power analysis (that tries to exploit additional information from the redundant bits) is rendered infeasible.

The field of computer hardware stands at the verge of a revolution driven by recent breakthroughs in emerging nanodevices. “Nano Security” is a new Priority Program recently approved by DFG, the German Research Council. This initial-stage project initiative at the crossroads of nano-electronics and hardware-oriented security includes 11 projects with a total of 23 Principal Investigators from 18 German institutions. It considers the interplay between security and nano-electronics, focusing on a dichotomy which emerging nano-devices (and their architectural implications) have on system security. The projects within the Priority Program consider both: potential security threats and vulnerabilities stemming from novel nano-electronics, and innovative approaches to establishing and improving system security based on nano-electronics. This paper provides an overview of the Priority Program's overall philosophy and discusses the scientific objectives of its individual projects.

Modern application-specific integrated circuits (ASICs) are increasingly employed in domains where they must fulfill security requirements. Traditional ASIC design flows include numerous steps to ensure the correctness of a circuit and its freedom from manufacturing defects, but they do not cover security vulnerabilities. In this paper, we show how to leverage state-of-the-art electronic design automation (EDA) tools to validate the resistance of a circuit against fault injection attacks in early design steps (before fabrication). While the approach is generic, we demonstrate it on a specific physical attack vector: Fault Sensitivity Analysis (FSA). We show how existing tools (especially for logic and timing simulation) can be extended by custom scripts to assess the vulnerability of an implementation to such attacks.

RISC-V has emerged as a viable solution on academia and industry. However, to use open source hardware for safety-critical applications, we need a deep understanding of the way in which well established mechanisms for testing and reliability could be integrated and deployed on the RISC-V ecosystem, and we need a clear knowledge on how such an ecosystem can be leveraged to improve security. This paper includes four contributions presenting the potential of RISC-V in security research, the way in which RISC-V can be hardened against power analysis attacks, how to implement, using RISC-V, software and hardware/software solutions for dual core lock step, and how to perform system-level testing in the RISC-V ecosystem.

While scalable, fully error corrected quantum computing is years or even decades away, there is considerable interest in noisy intermediate-scale quantum computing (NISQ). In this paper, we introduce the ArsoNISQ framework that determines the tolerable error rate of a given quantum algorithm computation, i.e. quantum circuits, and the success probability of the computation given a success criterion and a NISQ computer. ArsoNISQ is based on simulations of quantum circuits subject to errors according to the Pauli error model.ArsoNISQ was evaluated on a set of quantum algorithms that can incur a quantum speedup or are otherwise relevant to NISQ computing. Despite optimistic expectations in recent literature, we did not observe quantum algorithms with intrinsic robustness, i.e. algorithms that tolerate one error on average, in this evaluation. The evaluation demonstrated, however, that the quantum circuit size sets an upper bound for its tolerable error rate and quantified the difference in tolerate error rates for quantum circuits of similar sizes. Thus, the framework can assist quantum algorithm developers in improving their implementation and selecting a suitable NISQ computing platform. Extrapolating the results into the quantum advantage regime suggests that the error rate of larger quantum computers must decrease substantially or active quantum error correction will need to be deployed for most of the evaluated algorithms.

Quantum algorithms promise quadratic or exponential speedups for applications in cryptography, chemistry and material sciences. The topologies of today's quantum computers offer limited connectivity, leading to significant overheads for implementing such quantum algorithms. One-dimensional topology displacements that remedy these limits have been recently demonstrated for architectures based on Rydberg atoms, and they are possible in principle in photonic and ion trap architectures. We present the first optimal quantum circuit-to-architecture mapping algorithm that exploits such one-dimensional topology displacements. We benchmark our method on quantum circuits with up to 15 qubits and investigate the improvements compared with conventional mapping based on inserting swap gates into the quantum circuits. Depending on underlying technology parameters, our approach can decrease the quantum circuit depth by up to 58% and increase the fidelity by up to 29%. We also study runtime and fidelity requirements on one-dimensional displacements and swap gates to derive conditions under which one-dimensional topology displacements provide benefits.

System-level test (SLT) is gaining in importance in modern test flows. This paper summarizes recent industrial findings from three companies and discusses some of the still open questions. The first two reports focus on the optimization potentials due to defect coverage overlaps between SLT and other test insertions. Results observed on approximately 20 million manufactured 28nm and 40nm automotive system-on-chip (SoC) designs are reported. Costs and benefits of SLT are discussed and the potentials of a test results analytics platform are identified. The third report explores the role of marginalities among SLT fails. The post-silicon investigation of a CPU block in a 7nm 5G mobile SoC product aims at achieving a better understanding, whose fails are due to random variations versus systematic factors.

Breakthroughs in Deep neural networks (DNNs) steadily bring new innovations that substantially improve our daily life. However, DNNs overwhelm our existing computer architectures because the latter is largely bottlenecked by the data movement between memory and processing units. As a matter of fact, in the current von-Neumann architecture, which has remained unchanged since the beginning, data repeatedly moves back and forth between the physically-separated processing units (e.g., CPU, accelerator, etc.) and memory. This, in turn, inevitably leads to large latency and efficiency losses. In DNNs such a bottleneck becomes more and more prominent due to the massive amount of data that must be frequently transferred. This paper provides a cross-layer overview on how post-von-Neumann in-memory computing (IMC) architectures can be realized using three different emerging technologies: Charge-based ferroelectric transistors for logic-in-memory computations; memristive devices for unconventional brain-inspired computing; and ultra-low-power memristors especially suitable for Edge AI. Various levels of abstraction will be covered starting from semiconductor device physics to circuit and microarchitecture levels all the way up to the system level, but special attention will be put on reliability aspects.

With technology scaling approaching atomic levels, IC test and diagnosis of complex System-on-Chips (SoCs) become overwhelming challenging. In addition, sustaining the reliability of transistors as well as circuits at such extreme feature sizes, for the entire projected lifetime, also become profoundly difficult. This holds even more when it comes to emerging technologies that go beyond convectional CMOS in which the underlying physics are not yet fully understood. In this special session paper, we describe the usage of machine learning in several test and reliability related areas. First, we demonstrate the vital role that machine learning can play in IC test showing the importance of explainability as a frontier for machine learning in IC test. Afterwards, we discuss how novel physics-informed neural networks can be employed to model electrostatic problems in VLSI designs. This is essential to mitigate the deleterious effects of of time dependent dielectric breakdown, which is the key source of reliability degradations. Finally, we discuss the major sources of reliability degradations at the transistor level in advanced technology nodes such as transistor aging phenomena and self-heating effects as well as we demonstrate how machine learning approaches can further help in developing reliable emerging technologies.

First quantum computers very recently have demonstrated “quantum supremacy” or “quantum advantage Executing a computation that would have been impossible on a classical machine. Today's quantum computers follow the NISQ paradigm: They exhibit error rates that are much higher than in conventional electronics and have insufficient quantum resources to support powerful error correction protocols. This raises questions which relevant computations are within the reach of NISQ architectures. Several NISQ-era algorithms” are assumed to match the specifics of such computers; for instance, variational optimisers are based on intertwining relatively short quantum and classical computations, thus maximizing the chances of success. This paper will critically assess the promise and challenge of NISQ computing. What has this field achieved so far, what are we likely to achieve soon, where do we have to be skeptical and wait for the advent of larger-scale fully error-corrected architectures?

introduction Introduction to the Special Issue on Emerging Challenges and Solutions in Hardware Security Share on Editors: Domenic Forte View Profile , Debdeep Mukhopadhyay View Profile , Ilia Polian View Profile , Yunsi Fei View Profile , Rosario Cammarota View Profile Authors Info & Claims ACM Journal on Emerging Technologies in Computing SystemsVolume 17Issue 3July 2021 Article No.: 29pp 1–4https://doi.org/10.1145/3464326Online:30 June 2021Publication History 0citation108DownloadsMetricsTotal Citations0Total Downloads108Last 12 Months108Last 6 weeks4 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

System-level test, or SLT, is an increasingly important process step in today's integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in operational modes. In this paper, we consolidate available knowledge about what SLT is precisely and why it is used despite its considerable costs and complexities. We discuss the types or failures covered by SLT, and outline approaches to quality assessment, test generation and root-cause diagnosis in the context of SLT. Observing that the theoretical understanding for all these questions has not yet reached the level of maturity of the more conventional structural and functional test methods, we outline new and promising directions for methodical developments leveraging on recent findings from software engineering.

Modern electronic systems become evermore complex, yet remain modular, with integrated circuits (ICs) acting as versatile hardware components at their heart. Electronic design automation (EDA) for ICs has focused traditionally on power, performance, and area. However, given the rise of hardware-centric security threats, we believe that EDA must also adopt related notions like secure by design and secure composition of hardware. Despite various promising studies, we argue that some aspects still require more efforts, for example: effective means for compilation of assumptions and constraints for security schemes, all the way from the system level down to the "bare metal"; modeling, evaluation, and consideration of security-relevant metrics; or automated and holistic synthesis of various countermeasures, without inducing negative cross-effects.In this paper, we first introduce hardware security for the EDA community. Next we review prior (academic) art for EDA-driven security evaluation and implementation of countermeasures. We then discuss strategies and challenges for advancing research and development toward secure composition of circuits and systems.

Approximate computing is an architectural paradigm where limited and controlled errors during computation are tolerated. Thanks to approximation, circuits can be faster, more compact, and consume less power. Security aspects of these circuits are however largely unexplored. In this paper we focus on the problem of side channel attacks, and we discuss how they can be different when carried out in approximated circuits. We conclude our work highlighting challenges and possible research directions in this area.

Machine learning techniques have significantly changed our lives. They helped improving our everyday routines, but they also demonstrated to be an extremely helpful tool for more advanced and complex applications. However, the implications of hardware security problems under a massive diffusion of machine learning techniques are still to be completely understood. This paper first highlights novel applications of machine learning for hardware security, such as evaluation of post quantum cryptography hardware and extraction of physically unclonable functions from neural networks. Later, practical model extraction attack based on electromagnetic side-channel measurements are demonstrated followed by a discussion of strategies to protect proprietary models by watermarking them.

Stochastic computing (SC) with its small area and power footprint is a prime candidate for realizing neural networks (NNs) in heavily resource-restricted devices, such as near-sensor computing systems. Complete SCNNs encompassing all network layers have mostly been simulated in software, or synthesized without consideration of potential area limitations. In this work, we present a full FPGA implementation of a complete SCNN for image classification under tight resource constraints. All computational operations of the NN are performed on FPGA primitives. Furthermore, no DSPs and no onboard CPU is required for the computation. Our system operates at 60MHz and can classify an input image within approximately 6ms. Moreover, our basic SC and memory components can be flexibly combined to cover a large variety of NN structures.

Stochastic circuits (SCs) offer significant area, power and energy benefits at the cost of computational inaccuracies. SCs have received particular attention recently in the context of neural networks (NNs). Many NNs use the maximum function, e.g., in the max-pooling layer of convolutional NNs. Currently, approximate workarounds are often employed for this function. We propose NMax, a new SC design for the maximum function that produces an exact result with latency similar to an approximate circuit. Furthermore, unlike most stochastic functions, NMax is correlation insensitive. We also observe that maximum calculations are subject to application-specific bias and analyze this bias.

Autonomous systems promise solutions to a wide range of technical and societal problems, and their use appears especially attractive in safety-critical domains, like transportation or factory automation. This paper focuses on an underestimated aspect of autonomous systems: their security implications. Many approaches to design traditional secure systems do not readily transfer to autonomous systems, due to their high complexity and exposure to a broad spectrum of threats. Moreover, autonomous systems are often designed to be extremely long-living, and any security solutions should anticipate future threats to some extent. This paper starts with an overview of security threats applicable to autonomous systems and today's countermeasures to address these threats. Then, two representative techniques are elucidated in more detail: the use of post-quantum cryptography to achieve secure communication, and remote attestation as one essential building block for platform security.

The evaluation of fault attacks on security-critical hardware implementations of cryptographic primitives is an important concern. In such regards, we have created a framework for automated construction of fault attacks on hardware realization of ciphers. The framework can be used to quickly evaluate any cipher implementations, including any optimisations. It takes the circuit description of the cipher and the fault model as input. The output of the framework is a set of algebraic equations, such as conjunctive normal form (CNF) clauses, which is then fed to a SAT solver. We consider both attacking an actual implementation of a cipher on an field-programmable gate array (FPGA) platform using a fault injector and the evaluation of an early design of the cipher using idealized fault models. We report the successful application of our hardware-oriented framework to a collection of ciphers, including the advanced encryption standard (AES), and the lightweight block ciphers LED and PRESENT. The corresponding results and a discussion of the impact to different fault models on our framework are shown. Moreover, we report significant improvements compared to similar frameworks, such as speedups or more advanced features. Our framework is the first algebraic fault attack (AFA) tool to evaluate the state-of-the art cipher LED-64, PRESENT and full-scale AES using only hardware-oriented structural cipher descriptions.

Approximate computing promises significant advantages over more traditional computing architectures with respect to circuit area, performance, power efficiency, flexibility, and cost. Its use is suitable in applications where limited and controlled inaccuracies are tolerable or uncertainty is intrinsic in input or their data processing, e.g., as it happens in (deep-) machine learning, image and signal processing. This paper discusses a dimension of approximate computing that has been neglected so far, despite it represents nowadays a major asset, that of security. A number of hardware-related security threats are considered, and the implications of approximate circuits or systems designed to address these threats are discussed.

Stochastic circuits (SCs) offer considerable area- and power-consumption benefits in various applications at the expense of computational inaccuracies. Unlike conventional logic synthesis, managing accuracy is a central problem in SC design. It is usually tackled in ad hoc fashion by multiple trial-and-error simulations that vary relevant parameters like the stochastic number length n . We present, for the first time, a systematic design approach to controlling the accuracy of SCs and balancing it against other design parameters. We express the (in)accuracy of a circuit processing n -bit stochastic numbers by the numerical deviation of the computed value from the expected result, in conjunction with a confidence level. Using the theory of Monte Carlo simulation, we derive expressions for the stochastic number length required for a desired level of accuracy or vice versa. We discuss the integration of the theory into a design framework that is applicable to both combinational and sequential SCs. We show that for combinational SCs, accuracy is independent of the circuit’s size or complexity, a surprising result. We also show how the analysis can identify subtle errors in both combinational and sequential designs. Finally, we apply the proposed methods to a case study on filtering noisy EKG signals.

The cyber-physical system (CPS) paradigm offers tremendous advantages in many application scenarios and promises a solution to a large number of pressing individual and societal needs. However, their properties such as heterogeneity, lack of perimeter protection, longevity, pervasive diffusion and strictly constrained resources also give rise to new security vulnerabilities. In this paper, we discuss security threats related to the hardware blocks of a CPS. We first review attack scenarios affecting security attributes confidentiality, integrity and authenticity, and then outline novel attack vectors that target the cyber and the physical aspects of a CPS simultaneously.

Modern System-on-Chips rely heavily on the performance of their embedded memories which are also most susceptible to the increasing reliability challenges of today's nanoscale technology nodes. However, in contrast to memory core-cells, the effects of transistor aging inside the peripheral logic of SRAM architectures have received little attention. This study works out how BTI and HCI induced wear-out of the peripheral SRAM circuitry impacts various performance metrics of an industrially used memory library. We show that the degradation of the peripheral logic is the dominant driver for access speed loss while it tends to slightly lower memory read margin and lead to minor improvements of write margin. We furthermore show that in terms of access time margin the degradation of SRAM control circuitry counteracts aging effects inside core-cells and sense amplifiers. Surprisingly, wear-out of peripheral circuitry can even improve access time margin in case when the relative magnitude of PBTI is much lower compared with NBTI. Based on the example of an embedded memory library, this study further underlines the importance to analyze aging mechanisms at system level rather than for its individual interacting sub-circuits.

Stochastic circuits (SCs) offer tremendous areaand power-consumption benefits at the expense of computational inaccuracies. Managing accuracy is a central problem in SC design and has no counterpart in conventional circuit synthesis. It raises a basic question: how to build a systematic design flow for stochastic circuits? We present, for the first time, a systematic design approach to control the accuracy of SCs and balance it against other design parameters. We express the (in)accuracy of a circuit processing n-bit stochastic numbers by the numerical deviation of the computed value from the expected result, in conjunction with a confidence level. Using the theory of Monte Carlo simulation, we derive expressions for the stochastic number length required for a desired level of accuracy, or vice versa. We discuss the integration of the theory into a design framework that is applicable to both combinational and sequential SCs. We show that for combinational SCs, accuracy is independent of the circuit's size or complexity, a surprising result. We also show how the analysis can identify subtle errors in both combinational and sequential designs.

Physical unclonable functions (PUFs) can be used for a number of security applications, including secure on-chip generation of secret keys. We introduce an embedded PUF concept called sensitized path PUF (SP-PUF) that is based on extracting entropy out of inherent timing variability of modules already present in the circuit. The new PUF sensitizes paths of nearly identical lengths and generates response bits by racing transitions through different paths against each other. SP-PUF has lower area overhead and higher speed than earlier embedded PUFs and requires no helper data stored in non-volatile memory beyond standard error-correction information for fuzzy extraction. Compared with standalone PUFs, the new solution intrinsically and inseparably intertwines PUF behavior with functional circuitry, thus complicating invasive attacks or simplifying their detection. We present a systematic design flow to turn an arbitrary (sufficiently complex) circuit into an SP-PUF. The flow leverages state-of-the-art sensitization algorithms, formal filtering based on statistical analysis, and MaxSAT-based optimization of SP-PUF's area overhead. Experiments show that SP-PUF extracts 256-bit keys with perfect reliability and nearly perfect uniqueness after fuzzy extraction for the majority of standard benchmark circuits.

Stochastic circuits (SCs) offer tremendous area and power-consumption benefits at the expense of computational inaccuracies. They require random num-ber sources (RNSs) to implement stochastic number generators (SNGs) for all of their inputs. It is common for an SC to have a large number of primary and auxiliary inputs. Often the associated SNGs take up as much as 80% of the entire circuit area, so sharing RNSs is a very important goal in stochastic computing. Such sharing often leads to large correlation errors that have to be resolved via costly decorrelation methods. Linear feed-back shift registers (LFSRs) are typically used as RNSs. However, we show that their deterministic and linear behavior can interfere with commonly used decorrelation methods, causing systematic computation errors, and limiting the possibilities of sharing LFSRs between SNGs. We therefore propose a novel pseudo-random number generator SBoNG for stochastic circuits that combines an LFSR with a non-linear S-box function. An SBoNG does not interfere with decorrelation and can be shared effi-ciently by multiple SNGs. Consequently, SBoNGs scale very well in SCs with large numbers of inputs.

In the area of testing, faults represent defects that occur during circuit manufacturing, or transient disturbances due to radiation or noise. This paper provides an introduction into the area of fault-injection attacks, that is, faults that an attacker deliberately injects into a security-critical circuit. We will explain the threats posed by fault-injection attacks, pointing out similarities and differences between “natural” and malicious faults, and detection methods and countermeasures applicable in both cases. We will describe various methods of malicious fault injection with high and low precision and discuss the necessary equipment (including commercially available solutions), as well as potential impact of such faults to system security. In particular, we will discuss the relationship of fault-injection attacks with other attack vectors and with test and measurement techniques.

A prototype of the framework AutoFault, which automatically constructs fault-injection attacks for hardware realizations of ciphers, is presented. AutoFault can be used to quickly evaluate the resistance of security-critical hardware blocks to fault attacks and the adequacy of implemented countermeasures. The framework takes as inputs solely the circuit description of the cipher and the fault(s) and produces an algebraic formula that can be handed over to an external solver. In contrast to previous work, attacks constructed by AutoFault do not incorporate any cipher-specific cryptoanalytic derivations, making the framework accessible to users without cryptographic background. We report successful application of AutoFault in combination with a state-of-the-art SAT solver to LED-64 and to small-scale AES. To the best of our knowledge, this is the first time that a state-of-the-art cipher (LED-64) was broken by a fault attack with no prior manual cryptanalysis whatsoever.

Detailed knowledge of a circuit's timing is essential for performance optimization, timing closure, and generation of test patterns to detect small-delay defects. When an input transition is applied to the circuit's inputs, the resulting delay is not only determined by the propagation path, but also influenced by the power-supply noise. We introduce a path-sensitization procedure which precisely controls the switching activity in the circuit region surrounding the path. The procedure can maximize or minimize switching activity, or set it to a user-specified value. We study the accuracy-vs.-efficiency trade-offs for a hierarchy of timing models, from coarse zero-delay assumption to a waveform-accurate approach with sub-cycle resolution. For the first time, we present a MaxSAT formulation which guarantees maximization or minimization of switching activity, stemming from transitions and from glitches, simultaneously with path sensitization. We validate the quality of the generated test patterns using a mixed-mode IR-drop-aware timing simulator.

The transient voltage collapse (TVC) write-assist technique has emerged as a powerful method to enable low-voltage SRAM operation. However, it comes at the expense of higher complexity and vulnerability to errors as the additional peripheral circuitry is exposed to manufacturing defects. In this work, we analyze the TVC technique from a testing point of view. We study the effects of resistive-open defects inside the TVC circuitry and report the presence of a novel SRAM failure mechanism which occurs when the maximum voltage collapse level is not clamped to a fixed value. Finally, an efficient March test solution detecting these defects is presented.

Knowledge about sensitizable paths through combinational logic is essential for numerous design tasks. We present the framework PHAETON which identifies sensitizable paths and generates test pairs to exercise these paths using Boolean satisfiability (SAT). PHAETON supports a large number of models and sensitization conditions and provides a generic interface that can be used by applications. It incorporates a novel application-specific unary representation of integer numbers to integrate timing information with logical conditions within the same monolithic SAT formula. Due to a number of further elaborate speed-up techniques, PHAETON scales to industrial circuits. Experimental results show the performance of PHAETON in classical K longest path generation tasks and in new post-silicon validation and characterization scenarios.

As technology scales down, the density of SRAM devices increases drastically, and their storage capacity grows at the same time. Moreover, SRAMs become more prone to physical defects in each technology node, which therefore increases the need of effective tests with high fault coverage. It has been shown that resistive-bridging defects induce coupling faults that may increase defective parts per million levels if not well covered during manufacturing test. In this work, we study the reuse of read and write assist techniques, commonly applied to improve the functional margins of SRAM core-cells, to improve the coverage of coupling faults. This analysis is based on extensive injection of resistive bridging defects in core-cells of a commercial low-power SRAM. We show that assist circuits can be leveraged to increase the sensitization of defects causing coupling faults by 10-12%, however, they need to be used carefully.

Building a quantum computer that is sufficiently large for solving classically intractable computational problem instances is a grand challenge of today's science. The main fundamental obstacle to construction of scalable quantum computers is the vulnerability of their extremely fragile components to noise and decoherence due to environment interaction. This paper focuses on design of technology-independent quantum circuit architectures that are scalable and reliable as well as well-suited for physical implementation. The considered architectures will be protected against errors by state-of-the-art topological quantum error-correcting (TQEC) codes which combine a number of properties enabling the best scalability among all discussed alternatives. The theory of TQEC is very mature, the suitable hardware has made significant progress in recent years, and therefore the software challenges constitute the research gaps. We explain the abstraction levels which lay the foundation for systematic, top-down design automation methods for TQEC computers, discuss the appropriate optimization objectives and formulate a number of largely open design automation problems in this fields.

Vulnerability to malicious fault attacks is an emerging concern for hardware circuits that are employed in mobile and embedded systems and process sensitive data. We describe a new methodology to assess the vulnerability of a circuit to such attacks, taking into account built-in protection mechanisms. Our method is based on accurate modeling of fault effects and detection status expressed by Boolean satisfiability (SAT) formulas. Vulnerability is quantified based on the number of solutions of these formulas, which are determined by an efficient #SAT solver. We demonstrate the applicability of this method for design space exploration of a pseudo random number generator and for calculating the attack success rate in a multiplier circuit protected by robust error-detecting codes.

The realisation of large-scale quantum computing is no longer simply a hardware question. The rapid development of quantum technology has resulted in dozens of control and programming problems that should be directed towards the classical computer science and engineering community. One such problem is known as Pauli tracking. Methods for implementing quantum algorithms that are compatible with crucial error correction technology utilise extensive quantum teleportation protocols. These protocols are intrinsically probabilistic and result in correction operators that occur as byproducts of teleportation. These byproduct operators do not need to be corrected in the quantum hardware itself, but are tracked through the circuit and output results reinterpreted. This tracking is routinely ignored in quantum information as it is assumed that tracking algorithms will eventually be developed. In this work we help fill this gap and present an algorithm for tracking byproduct operators through a quantum computation.

Multiantenna telecommunication systems represent channels with multiple inputs and multiple outputs (MIMO) by matrices. QR decomposition (QRD) of the channel matrix is a crucial part of MIMO detection algorithms, such as successive interference cancellation or sphere detection. Modern standards like Long Term Evolution (LTE) require the processing of millions of matrices per second, in order to compensate channel changes that occur due to the mobility of the detector and Doppler spread. We introduce a new architecture for minimum mean square error (MMSE) sorted QR decomposition based on Givens rotations. The architecture is derived from classical systolic array approach but includes modifications to allow sorting and MMSE preprocessing. It balances throughput against area and fulfills the real-time requirements of 1.763 μs and 0.881 μs derived from the LTE MIMO standard when synthesized on ALTERA Stratix III and Stratix V family FPGAs. Moreover, it can trade speed for area and is suitable for tighter time constraints.

The rapidly increasing variability in circuit performance in highly scaled technologies has given rise to novel “better-than-worst-case” circuit design methods. They aim to overcome worst-case clock timing requirements by employing a shorter clock period and allowing occasional errors to occur; these are detected and recovered from by low-cost error detection and correction techniques. We investigate conditions under which timing error detection based on the memory element duplication with delayed capture is reliable even under extreme variations, where the key problem arises from short-path invalidation mechanisms. We consider two known mitigation techniques: buffer padding and latch placement. The derived conditions can yield the interval of clock periods within which an adaptive frequency scaling strategy may reliably operate. We show that buffer padding is impossible if variability exceeds a certain limit, but latch placement always yields a solution, works for more clock frequencies, and tends to incur less area costs, at the cost of clock power.

In technologies affected by variability, the detection status of a small-delay fault may vary among manufactured circuit instances. The same fault may be detected, missed or provably undetectable in different circuit instances. We introduce the first complete flow to accurately evaluate and systematically maximize the test quality under variability. As the number of possible circuit instances is infinite, we employ statistical analysis to obtain a test set that achieves a fault-efficiency target with an user-defined confidence level. The algorithm combines a classical path-oriented test-generation procedure with a novel waveform-accurate engine that can formally prove that a small-delay fault is not detectable and does not count towards fault efficiency. Extensive simulation results demonstrate the performance of the generated test sets for industrial circuits affected by uncorrelated and correlated variations.

We propose two extremely stealthy hardware Trojans that facilitate fault-injection attacks in cryptographic blocks. The Trojans are carefully inserted to modify the electrical characteristics of predetermined transistors in a circuit by altering parameters such as doping concentration and do pant area. These Trojans are activated with very low probability under the presence of a slightly reduced supply voltage (0.001 for 20% Vdd reduction). We demonstrate the effectiveness of the Trojans by utilizing them to inject faults into an ASIC implementation of the recently introduced lightweight cipher PRINCE. Full circuit-level simulation followed by differential cryptanalysis demonstrate that the secret key can be reconstructed after around 5 fault-injections.

State-of-the-art fault-based cryptanalysis methods are capable of breaking most recent ciphers after only a few fault injections. However, they require temporal and spatial accuracies of fault injection that were believed to rule out low-cost injection techniques such as voltage, frequency or temperature manipulation. We investigate selection of supply-voltage and temperature values that are suitable for high-precision fault injection even up to a single bit. The object of our studies is an ASIC implementation of the recently presented block cipher PRINCE, for which a two-stage fault attack scheme has been suggested lately. This attack requires, on average, about four to five fault injections in well-defined locations. We show by electrical simulations that voltage-temperature points exist for which faults show up at locations required for a successful attack with a likelihood of around 0.1%. This implies that the complete attack can be mounted by approximately 4,000 to 5,000 fault injection attempts, which is clearly feasible.

Circuits that employ test pattern compression rely on test cubes to achieve high compression ratios. The less inputs of a test pattern are specified, the better it can be compacted and hence the lower the test application time. Although there exist previous approaches to generate such test cubes, none of them are optimal. We present for the first time a framework that yields provably optimal test cubes by using the theory of quantified Boolean formulas (QBF). Extensive comparisons with previous methods demonstrate the quality gain of the proposed method.

IR-drop effects are increasingly relevant in context of both design and test. We introduce the event-driven simulator MIRID that calculates the impact of IR-drop to the circuit timing. MIRID performs the simulation on two abstraction levels: timing effects in the gate-level net-list, current and voltage waveform propagation in the electrical model of the power-distribution network (PDN). Switching events at the logic gates are forwarded to the electrical model, where induced currents and their impact on the neighboring PDN nodes are computed. From this information, values of voltages at the Vdd and ground terminals of logic gates are determined, which in turn are used to calculate accurate switching delays of the gates. MIRID supports a generic interface to electrical models, allowing for a seamless integration of arbitrary models of PDN and gate timing. We report experiments based on a simple PDN model that was introduced previously and incorporates a pre-characterized library. The simulation accuracy is validated by matching the results from MIRID and SPICE.

Comprehensive coverage of small-delay faults under massive process variations is achieved when multiple paths through the fault locations are sensitized by the test pair set. Using one test pair per path may lead to impractical test set sizes and test application times due to the large number of near-critical paths in state-of-the-art circuits.

Mobile and embedded systems increasingly process sensitive data, ranging from personal information including health records or financial transactions to parameters of technical systems such as car engines. Cryptographic circuits are employed to protect these data from unauthorized access and manipulation. Fault-based attacks are a relatively new threat to system integrity. They circumvent the protection by inducing faults into the hardware implementation of cryptographic functions, thus affecting encryption and/or decryption in a controlled way. By doing so, the attacker obtains supplementary information that she can utilize during cryptanalysis to derive protected data, such as secret keys. In the recent years, a large number of fault-based attacks and countermeasures to protect cryptographic circuits against them have been developed. However, isolated techniques for each individual attack are no longer sufficient, and a generic protective strategy is lacking.

Integrated circuit counterfeiting is a severe challenge for semiconductor companies, system integrators and product end-users. Substantial revenue losses by individual enterprises as well as detrimental economy-wide effects have triggered significant interest in counterfeit detection and prevention by commercial actors and governments. This resulted in a number of large-scale research initiatives and networks that focus on this topic, in North America, Europe and elsewhere. The hot-topic special session will introduce the test community to counterfeit detection techniques and identify open problems which can be solved using tools and methods from the testing area.

A new approach to detecting and diagnosing faults in quantum circuits is introduced. In order to account for the probabilistic nature of quantum circuits, collections of test experiments, called binary tomographic tests (BTTs), are generated. A BTT can identify a fault with respect to some user-defined confidence threshold τ. We present an algorithm to generate BTTs that either detect, or ensure the absence of, all modeled faults in a given circuit. We also present an adaptive diagnostic method to locate quantum faults. While classical circuits, even probabilistic ones, only handle ordinary probabilities, quantum circuits deal with quantum states, which have phase as an extra probabilistic parameter. The tomographic testing methods introduced previously for probabilistic circuits are unable to detect differences in phase, and therefore leave many quantum faults undetected. In contrast, we develop a design-for-test method which is specifically intended to detect faults that only affect the phase of a quantum state. We give experimental results for benchmark and random circuits which show high coverage of quantum faults by BTTs, and good resolution in the case of the adaptive diagnosis method.

An iterative flow to generate test sets providing high fault coverage under extreme parameter variations is presented. The generation is guided by the novel metric of circuit coverage, calculated by massively parallel statistical fault simulation on GPGPUs. Experiments show that the statistical fault coverage of the generated test sets exceeds by far that achieved by standard approaches.

Summary form only given. This special session will introduce the field to the design automation and test community, focusing on recent developments. The ultimate objective of the session is to initiate a dialogue with quantum informatics community by identifying open problems from quantum informatics which can be tackled by design automation methods such as synthesis, optimisation and verification. Among the four speakers are physicists as well as design automation researchers already working on problems from the quantum informatics domain. The first talk of the session will be given by Professor Rodney Van Meter of Keio University, Fujisawa. He will introduce quantum circuits, focusing on the non-trivial aspects of estimating the implementation cost of a given quantum circuit. Such metrics, which roughly correspond to the circuit’s area in the classical domain, will be of highest importance for any quantum circuit optimisation algorithm. Professor Simon Devitt of the National Institute of Informatics, Tokyo, will introduce the concept of topological quantum computing, which is the foundation of most recent scalable quantum circuit implementations. The third speaker, Professor Shigeru Yamashita of Ritsumeikan University, Shiga, will present his recent results on circuit-level optimisation of topological quantum circuits. The problem instances are mapped to a graph, and the optimisation is performed by identifying maximal cliques in this graph. Finally, Professor Austin Fowler of University of Melbourne will speak on recent developments in quantum error correcting codes and classical challenges that arise in this domain. The first three presentations have accompanying papers that are included in the proceedings.

Adequate coverage of small-delay defects in circuits affected by statistical process variations requires identification and sensitization of multiple paths through potential defect sites. Existing K longest path generation (KLPG) algorithms use a data structure called path store to prune the search space by restricting the number of sub-paths considered at the same time. While this restriction speeds up the KLPG process, the algorithms lose their optimality and do not guarantee that the K longest sensitizable paths are indeed found. We investigate, for the first time, the effects of missing some of the longest paths on the defect coverage. We systematically quantify how setting different limits on the path-store size affects the numbers and relative lengths of identified paths, as well as the run-times of the algorithm. We also introduce a new optimal KLPG algorithm that works iteratively and pinpointedly addresses defect locations for which the path-store size limit has been exceeded in previous iterations. We compare this algorithm with a naïve KLPG approach that achieves optimality by setting the path-store size limit to a very large value. Extensive experiments are reported for 45nm-technology data.

Power droop is a non-trivial signal-integrity-related effect triggered by specific power-supply conditions. High-frequency and low-frequency power droop may lead to failure of an IC during application time, but they usually remain undetected by state-of-the-art manufacturing test methods, as the fault excitation imposes particular conditions on global switching activity over several time frames. Hence, ATPG for power-droop test (PD-ATPG) is an extremely hard problem that has not yet been solved optimally. In this paper, we use a SAT-based ATPG engine that employs a mechanism known as SAT-solving with qualitative preferences to generate a solution guaranteed to be optimal for a given set of optimisation criteria, however at the expense of high SAT-solving times. Therefore, a well-balanced set of criteria has to be chosen for the SAT-formulation in order to get as good solutions as possible without rendering the SAT-instances impracticably hard. We explore several strategies and evaluate them experimentally.

Post-silicon validation, i.e., physical characterization of a small number of fabricated circuit instances before start of high-volume manufacturing, has become an essential step in integrated circuit production. Post-silicon validation is required to identify intricate logic or electrical bugs which could not be found during pre-silicon verification. In addition, physical characterization is useful to determine the performance distribution of the manufactured circuit instances and to derive performance yield. Test vectors used for this step are subject to different requirements compared to vectors for simulation-based verification or for manufacturing test. In particular, they must sensitize a very comprehensive set of paths in the circuit, assuming massive variations and possible modeling deficiencies. An inadequate test vector set may result in overly optimistic yield estimates and wrong manufacturing decisions. On the other hand, the size of the test vector set is less important than in verification or manufacturing test. In this paper, we systematically investigate the relationship between the quality of the employed test vectors and the accuracy of yield-performance predictions. We use a highly efficient SAT-based algorithm to generate comprehensive test vector sets based on simple model assumptions and validate these test sets using simulated circuit instances which incorporate effects of process variations. The obtained vector sets can also serve as a basis for adaptive manufacturing test.

The detection of small-delay faults is traditionally performed by sensitizing transitions on a path of sufficient length from an input to an output of the circuit going through the fault site. While this approach allows efficient test generation algorithms, it may result in false positives and false negatives as well, i.e. undetected faults are classified as detected or detectable faults are classified as undetectable. We present an automatic test pattern generation algorithm which considers waveforms and their propagation on each relevant line of the circuit. The model incorporates individual delays for each gate and filtering of small glitches. The algorithm is based on an optimized encoding of the test generation problem by a Boolean satisfiability (SAT) instance and is implemented in the tool WaveSAT. Experimental results for ISCAS-85, ITC-99 and industrial circuits show that no known definition of path sensitization can eliminate false positives and false negatives at the same time, thus resulting in inadequate small-delay fault detection. WaveSAT generates a test if the fault is testable and is also capable of automatically generating a formal redundancy proof for undetectable small-delay faults; to the best of our knowledge this is the first such algorithm that is both scalable and complete.

Nanoscale electronics is increasingly affected by disturbances caused by radiation, noise and effects of statistical process variations. Moreover, deliberate injection of faults into cryptographic circuits is used by malicious attackers to perform cryptanalysis and gain access to sensitive information. Error-detecting codes are employed to protect circuits against such disturbances, and new advanced codes specifically designed to counter malicious attacks have recently been introduced. However, a number of logic gates in the circuit are not adequately protected by the error-detecting code, as faults affecting these gates escape detection with a relatively high probability. We introduce a cross-level protection solution, where a light-weight error-detecting code is combined with hardening of insufficiently protected gates using transistor resizing. Such gates are determined by FPGA-supported fault injection. A thorough electrical analysis is performed in order to modify the electrical parameters of these gates such that faults are highly unlikely. We report area and power overhead for a number of error-detecting codes. To the best of our knowledge, this is the first work which co-optimizes fault handling by information redundancy based on error-detecting codes and by hardening individual circuit elements.

We present SATSEQ, a timing-aware ATPG system for small-delay faults in non-scan circuits. The tool identifies the longest paths suitable for functional fault propagation and generates the shortest possible sub-sequences per fault. Based on advanced model-checking techniques, SATSEQ provides detection of small-delay faults through the longest functional paths. All test sequences start at the circuit's initial state; therefore, overtesting is avoided. Moreover, potential invalidation of the fault detection is taken into account. Experimental results show high detection and better performance than scan testing in terms of test application time and overtesting-avoidance.

Failures caused by phenomena such as crosstalk or power-supply noise are gaining in importance in advanced nanoscale technologies. The detection of such complex defects benefits from the satisfaction of certain constraints, for instance justifying specific transitions on neighbouring lines of the defect location. We present a SAT-based ATPG-tool that supports the enhanced conditional multiple-stuck-at fault model (ECMS@). This model can specify multiple fault locations along with a set of hard conditions imposed on arbitrary lines; hard conditions must hold in order for the fault effect to become active. Additionally, optimisation constraints that may be required for best coverage can be specified via a set of soft conditions. The introduced tool justifies as many of these conditions as possible, using a mechanism known as SAT with preferences. Several applications are discussed and evaluated by extensive experimental data. Furthermore, a novel fault-clustering technique is introduced, thanks to which the time required to classify all stuck-at faults in a suite of industrial benchmarks was reduced by up to 65%.

We present a versatile method that enumerates all or a user-specified number of longest sensitisable paths in the whole circuit or through specific components. The path information can be used for design and test of circuits affected by statistical process variations. The algorithm encodes all aspects of the path search as an instance of the Boolean Satisfiability Problem (SAT), which allows the method not only to benefit from recent advances in SAT-solving technology, but also to avoid some of the drawbacks of previous structural approaches. Experimental results for academic and industrial benchmark circuits demonstrate the method's accuracy and scalability.

We present an energy-reduction strategy for applications which are resilient, i. e. can tolerate occasional errors, based on an adaptive voltage control. The voltage is lowered, possibly beyond the safe-operation region, as long as no errors are observed, and raised again when the severity of the detected errors exceeds a threshold. Due to the resilient nature of the applications, lightweight error detection logic is sufficient for operation, and no expensive error recovery circuitry is required. On a hardware block implementing texture decompression, we observe 25% to 30% energy reduction at negligible quality loss (compared to the error introduced by the lossy compression algorithm). We investigate the strategy's performance under temperature and process variations and different assumptions on voltage-control circuitry. The strategy automatically chooses the lowest appropriate voltage, and thus the largest energy reduction, for each individual manufactured instance of the circuit.

Manufacturing defects in nanoscale technologies have highly complex timing behaviour that is also affected by process variations. While conventional wisdom suggests that it is optimal to detect a delay defect through the longest sensitisable path, non-trivial defect behaviour along with modelling inaccuracies necessitate consideration of paths of well-controlled length during test generation. We present a generic methodology that yields tests through all sensitisable paths of user-specified length. The resulting tests can be employed within the framework of adaptive testing. The methodology is based on encoding the problem as a Boolean-satisfiability (SAT) instance and thereby leverages recent advances in SAT-solving technology.

Some emerging technologies for building computers depend on components and signals whose behavior, under normal or fault conditions, is probabilistic. Examples include stochastic and quantum computing circuits, and conventional nano electronic circuits subject to design, manufacturing or environmental errors. Problems common to these technologies are testing and validation, which require determining whether observed non-deterministic behavior is within acceptable limits. Traditional solution methods rely on the determinism of operations performed by the circuit under test, and are not applicable to probabilistic circuits, where signals are often described by probability distributions. We introduce a generic methodology for testing probabilistic circuits by approximating signal probability distributions using tomograms, which aggregate the outcomes of multiple, repeated test measurements. While the name comes from quantum computation, tomography is applicable to both quantum and non-quantum probabilistic circuits, as we demonstrate. Our methodology makes use of fault or error models that allow handling of large and complex circuits. We report the first experimental results on the tomographic testing of quantum and stochastic circuits.

Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality.

Nanoscale integrated circuits suffer both from high defect densities and increased parameter variations possibly affecting the overall timing behaviour. Components with a higher vulnerability to process variations are not just critical during test design and test application, but also during normal operation. In particular, ageing effects and changes in the operation environment including supply voltage, temperature and radiation, can easily aggravate the effects of parameter variations inherent to the manufacturing process. Online and offline techniques that attempt to cope with such effects, like online error detection and correction, online diagnosis and hardening, have high cost and therefore cannot be applied to the whole circuit. Making a good selection of components to apply these techniques to, requires accurate metrics for gate criticality under process variations. This paper presents a SAT-based approach to measure criticality. The algorithm requires a minimal amount of physical and electrical data, but it delivers a very good criticality estimate in a fraction of the time required by accurate statistical simulation. The results are validated by comparison to an exact simulation-based approach.

State-of-the-art cyber-physical systems are increasingly deployed in harsh environments with non-negligible soft error rates, such as aviation or search-and-rescue missions. State-of-the-art nanoscale manufacturing technologies are more vulnerable to soft errors. In this paper, we present an FPGA-based framework for injecting soft errors into user-specified memory elements of an entire microprocessor (MIPS32) running application software. While the framework is applicable to arbitrary software, we demonstrate its usage by characterizing soft errors effects on several software filters used in aviation for probabilistic sensor data fusion.

Transient or soft errors caused by various environmental effects are a growing concern in micro and nanoelectronics. We present a general framework for modeling and mitigating the logical effects of such errors in digital circuits. We observe that some errors have time-bounded effects; the system's output is corrupted for a few clock cycles, after which it recovers automatically. Since such erroneous behavior can be tolerated by some applications, i.e., it is noncritical at the system level, we define the critical soft error rate (CSER) as a more realistic alternative to the conventional SER measure. A simplified technology-independent fault model, the single transient fault (STF), is proposed for efficiently estimating the error probabilities associated with individual nodes in both combinational and sequential logic. STFs can be used to compute various other useful metrics for the faults and errors of interest, and the required computations can leverage the large body of existing methods and tools designed for (permanent) stuck-at faults. As an application of the proposed methodology, we introduce a systematic strategy for hardening logic circuits against transient faults. The goal is to achieve a desired level of CSER at minimum cost by selecting a subset of nodes for hardening against STFs. Exact and approximate algorithms to solve the node selection problem are presented. The effectiveness of this approach is demonstrated by experiments with the ISCAS-85 and -89 benchmark suites, as well as some large (multimillion-gate) industrial circuits.

To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simu-lations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defect-induced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45nm technology.

Low-power test aims at reduction of power-induced effects in the circuit under test in order to prevent overtesting. In contrast, noise-aware test attempts to maximize power noise to excite the chip in worst-case situations. Does low-power test potentially lead to test escapes? Will noise-aware test sort out chips which would never fail in their actual operation? What is the right approach, or the right mix of the approaches? Is the academia working on the right problems? This panel brings together experts from academia, semiconductor, EDA and IP industry.

SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compaction procedure for SAT-based ATPG which utilizes internal data structures of the SAT solver to extract essential fault detection conditions and to generate patterns which cover multiple faults. We complement this technique by a state-of-the-art forward-looking reverse-order simulation procedure. Experimental results obtained for an industrial benchmark circuit suite show that the new method outperforms earlier static approaches by approximately 23%.

In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques. We trade-off between selective hardening in hardware and process re-execution in software to provide the required levels of fault tolerance against transient faults with the lowest-possible system costs. We propose a system failure probability (SFP) analysis that connects the hardening level with the maximum number of re-executions in software. We present design optimization heuristics, to select the fault-tolerant architecture and decide process mapping such that the system cost is minimized, deadlines are satisfied, and the reliability requirements are fulfilled.

A significant increase in power density in modern nano-electronic VLSI circuits has lead to increased localized heating and generation of hot spots. These temperature effects can lead to reliability and performance problems. This paper presents a novel design time temperature aware methodology which consists of using additional routing known as Heat Pipes, to transfer heat from hot to cold regions. In order to evaluate the effect of Heat Pipes, a thermal model to simulate effect of metal interconnect on heat distribution is also developed. Results show a 5% to 7% decrease in temperature variation through-out and 2 to 3 degree reduction in hotspot temperature as a result of Heat Pipes.

Robust circuit design has become a major concern for nanoscale technologies. As a consequence, for design validation, not only the functionality of a circuit has to be considered, but also its robustness properties have to be analyzed. In this work we propose a method to verify the strong fault-secureness by use of constrained SAT-based ATPG. Strongly fault-secure circuits can be seen as the widest class of circuits achieving the totally self-checking (TSC) goal, which requires that every fault be detected the first time it manifests itself as an error at the outputs. As the strongly fault-secure property guarantees to achieve the TSC goal even in the case of fault accumulation, the effects of all possible fault sequences have to be taken into consideration to verify this property. To speed up the complex analysis of multiple faults we develop rules to derive detectability or redundancy information for multiple faults from the respective information for single faults. For the case of not strongly fault-secure circuits our method provides measures to grade the ldquoextentrdquo of strong fault-secureness given by the implementation.

In this paper a new electrical model is proposed to be used in fault size based fault simulation of crosstalk aggravated resistive short defects. The electrical behavior of the defect is first described and analyzed in details. Then an electrical model is proposed allowing to efficiently compute the critical resistance determining the range of detectable short resistance. The model is validated by comparison with SPICE simulations.

A high-performance resistive bridging fault simulator SUPERB (Simulator Utilizing Parallel Evaluation of Resistive Bridges) is proposed. It is based on fault sectioning in combination with parallel-pattern or parallel-fault multiple-stuck-at simulation. It outperforms a conventional interval-based resistive bridging fault simulator by three orders of magnitude while delivering identical results. Further competing tools are outperformed by several orders of magnitude. Industrial-size circuits, including a multi-million-gates design, could be simulated with runtimes within an order of magnitude of the runtimes for pattern-parallel stuck-at fault simulation.

We report the successful application of a resistive bridging fault (RBF) simulator to industrial benchmark circuits. Despite the slowdown due to the consideration of the sophisticated RBF model, the run times of the simulator were within an order of magnitude of the run times for pattern-parallel complete-circuit stuck-at fault simulation. Industrial-size circuits, including a multi-million-gates design, could be simulated in reasonable time despite a significantly higher number of faults to be simulated compared with stuck-at fault simulation.

Many classes of applications are inherently tolerant to errors. One such class are applications designed for a human end user, where the capabilities of the human cognitive system (cognitive resilience) may compensate some of the errors produced by the application. We present a methodology to automatically distinguish between tolerable errors in imaging applications which can be handled by the human cognitive system and severe errors which are perceptible to a human end user. We also introduce an approach to identify non-critical spots in a hardware circuit which should not be hardened against soft errors because errors that occur on these spots are tolerable. We demonstrate that over 50% of flip-flops in a JPEG compressor chip are non-critical and require no hardening.

We present a simulator which determines the coverage of small-delay faults, i.e., delay faults with a size below one clock cycle, caused by resistive-open defects. These defects are likely to escape detection by stuck-at or transition fault patterns. For the first time, we couple the calculation of the critical size of a small-delay fault with the computation of the resistance range of the corresponding resistive-open defect for which this size is exceeded. By doing so, we are able to extend probabilistic fault coverage metrics initially developed for static resistive bridging faults to small-delay defects.

Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority should be given to critical spots for which an error is likely to cause a system malfunction. The criticality of the spots depends on parameters not all available in early design steps. We employ a selection strategy which takes only gate-level information into account and does not use any low-level electrical or timing information. We validate the quality of the solution using an accurate SER estimator based on the new UGC particle strike model. Although only partial information is utilized for hardening, the exact validation shows that the susceptibility of a circuit to soft errors is reduced significantly. The results of the hardening strategy presented are also superior to known purely topological strategies in terms of both hardware overhead and protection.

We present a flow to extract, simulate and generate test patterns for interconnect open defects. In contrast to previous work, the accuracy of defect modeling is improved by taking the thresholds of logic gates as well as noise margins into account. Efficient fault simulation is enabled by employing an aggressive fault collapsing strategy and an optimized fault list ordering heuristic which allows to combine the advantages of event-driven simulation with bit parallelism. Test generation complexity is kept in check by generating patterns for technology-independent segment-stuck-at faults first, thus reducing (though not completely eliminating) the need for sophisticated technology-aware test generation. Moreover, a comprehensive untestability analysis identifies new classes of untestable faults. Experimental results demonstrate high efficiency of the new flow, outperforming earlier work by two orders of magnitude.

We present a fully automated flow to generate test patterns for interconnect open defects. Both inter-layer opens (open- via defects) and arbitrary intra-layer opens can be targeted. An aggressor-victim model used in industry is employed to describe the electrical behavior of the open defect. The flow is implemented using standard commercial tools for parameter extraction (PEX) and test generation (ATPG). A highly optimized branch-and bound algorithm to determine the values to be assigned to the aggressor lines is used to reduce both the ATPG efforts and the number of aborts. The resulting test sets are smaller and achieve a higher defect coverage than stuck-at n-detection test sets, and are robust against process variations.

Test application at reduced power supply voltage (low-voltage testing) or reduced temperature (low-temperature testing) can improve the defect coverage of a test set, particularly of resistive short defects. Using a probabilistic model of two-line nonfeedback short defects, we quantify the coverage impact of low-voltage and low-temperature testing for different voltages and temperatures. Effects of statistical process variations are not considered in the model. When quantifying the coverage increase, we differentiate between defects missed by the test set at nominal conditions and undetectable defects (flaws) detected at non nominal conditions. In our analysis, the performance degradation of the device caused by lower power supply voltage is accounted for. Furthermore, we describe a situation in which defects detected by conventional testing are missed by low-voltage testing and quantify the resulting coverage loss. Experimental results suggest that test quality is improved even if no cost increase is allowed. If multiple test applications are acceptable, a combination of low voltage and low temperature turns out to provide the best coverage of both hard defects and flaws.

A high-performance resistive bridging fault simulator SUPERB (Simulator Utilizing Parallel Evaluation of Resis- tive Bridges) is proposed. It is based on fault sectioning in combination with parallel-pattern or parallel-fault multiple- stuck-at simulation. It outperforms a conventional interval- based resistive bridging fault simulator by 60X to 120X while delivering identical results. Further competing tools are out- performed by several orders of magnitude.

Open-via defects are a major systematic failure mechanism in nanoscale manufacturing processes. We present a flow for simulating open-via defects. Electrical parameters are extracted from the layout and technology data and represented in a way which allows efficient simulation on gate level. The simulator takes oscillation caused by open-via defects into account and quantifies its impact on defect coverage. The flow can be employed for manufacturing test as well as for defect diagnosis.

Practical on-line test methods do not cover all possible faults of a system. We propose a method to identify critical faults and distinguish them from non-critical ones. Low-cost on-line fault detection can focus on the critical faults. Alternatively, the circuit sites associated with critical faults could be selectively hardened to improve the overall reliability of a system. This is done in a cost-effective way because no hardening against non-critical faults is required. In this work, we concentrate on faults in imaging applications such as video. We classify faults based on their impact on the system behavior, i.e., the visibility of their effects by a human end-user. The psychovisual model from the JPEG compression method is used for fault effect classification.

Transient or soft errors are an increasing problem in mainstream microelectronics. We propose a framework for modeling transient-error tolerance (TET) in logic circuits. We classify transient errors as critical or non-critical according to their impact on circuit behavior, such as their ability to disturb the internal state for specified periods of time. We introduce a metric called the critical soft-error rate (CSER) as an alternative to conventional SER, and present some analysis strategies based on CSER. This approach employs a new single transient fault (STF) model, which is defined in terms of a temporary stuck-at fault and its associated circuit state. Although basically technology-independent, STFs can be extended with low-level physical attributes. With STFs, we can estimate the transient error probability perrof a circuit's nodes, as well as various measures of error susceptibility and TET. We demonstrate the use of STFs with combinational and sequential circuits, including several types of adders. We also present a systematic hardening strategy that uses perras a guide to improving TET.

This paper addresses the efficiency of IDDQand more specifically Delta- IDDQtesting when using a realistic short defect model that properly considers the relation between the resistance of the short and its detectability. The results clearly show that the Delta-IDDQapproach covers a large number of resistive shorts missed by conventional logic testing, requiring only a relatively small vector set. In addition a significant number of defects which are proven to be undetectable by logic testing but may deteriorate and result in reliability failures are detected. The Delta- IDDQthreshold and thus the equipment sensitivity is shown to be critical for the test quality. Furthermore, the validity of the traditional IDDQfault models when considering resistive short defects is found to be limited. For instance, the use of the fault-free next-state function for sequential IDDQfault simulation is shown to result in a wrong classification of some resistive short defects. This is the first systematic study of IDDQtesting of resistive short defects. The impact of the threshold on the defect coverage is quantified for the first time. Although the simulation results are based upon a 0.35mum technology, the results and methodology can be transferred to state-of-the-art and NanoTechnologies

This paper analyzes the electrical behaviour of resistive opens as a function of their unpredictable resistance. It is demonstrated that the electrical behaviour depends on the value of the open resistance. It is also shown that detection of the open by a given vector Tirecursively depends on all the vectors that have been applied to the circuit before Ti. An electrical analysis of this recursive effect is presented and a specific ATPG strategy is proposed

We present an approach to prevent over testing in scan-based delay test. The test data is transformed with respect to functional constraints while simultaneously keeping as many positions as possible unspecified in order to facilitate test compression. The method is independent of the employed delay fault model, ATPG algorithm and test compression technique, and it is easy to integrate into an existing flow. Experimental results emphasize the severity of over testing in scan-based delay test. Influence of different functional constraints on the amount of the required test data and the compression efficiency is investigated. To the best of our knowledge, this is the first systematic study on the relationship between over testing prevention and test compression

Circuit activity is a function of input patterns. When circuit activity changes abruptly, it can cause sudden drop or rise in power supply voltage. This change is known as power droop and is an instance of power supply noise. Although power droop may cause an IC to fail, such failures cannot currently be screened during testing as it is not covered by conventional fault models. In this paper we present a technique for screening such failures. We propose a heuristic method to generate test sequences which create worst-case power drop by accumulating the high-frequency and low-frequency effects. The generated patterns need to be sequential even for scan designs. We employ a dynamically constrained version of the classical D-algorithm for test generation, i.e., the algorithm generates new constraints on-the-fly depending on previous assignments. The obtained patterns can be used for manufacturing testing as well as for early silicon validation. A prototype ATPG is implemented to demonstrate the feasibility of the approach and test sequences are generated for ISCAS circuits.

A significant fraction of soft errors in modern microprocessors has been reported to never lead to a system failure. Any concurrent error detection scheme that raises alarm every time a soft error is detected is not well heeded because most of these alarms are false and responding to them will affect system performance negatively. This paper improves state of the art in detecting and preventing false alarms. Existing techniques are enhanced by a methodology to handle soft errors on address bits. Furthermore, we demonstrate benefit of false alarm identification in implementing a roll-back recovery system by first calculating the optimum check pointing interval for a roll-back recovery system and then showing that the optimal number of check-points decreases by orders of magnitude when exclusion techniques are used even if the implementation of exclusion technique is not perfect

The authors present a simulator for resistive-bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look up, thus, exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; interaction of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive-bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed, and quantitative results with respect to all these definitions are given for the first time.

We present a technique for making a circuit ready for logic built-in self test by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.

Resistive defects are gaining importance in very-deepsubmicron technologies, but their detection conditions are not trivial. Test application can be performed under reduced temperature and/or voltage in order to improve detection of these defects. This is the first analytical study of resistive bridge defect coverage of CMOS ICs under low-temperature and mixed low-temperature, low-voltage conditions. We extend a resistive bridging fault model in order to account for temperature-induced changes in detection conditions. We account for changes in both the parameters of transistors involved in the bridge and the resistance of the short defect itself. Using a resistive bridging fault simulator, we determine fault coverage for low-temperature testing and compare it to the numbers obtained at nominal conditions. We also quantify the coverage of flaws, i.e. defects that are redundant at nominal conditions but could deteriorate and become earlylife failures. Finally, we compare our results to the case of low-voltage testing and comment on combination of these two techniques.

Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional circuits such as stuck-at models are not wellsuited to quantum circuits. We derive a family of logical fault models for reversible circuits composed of k- CNOT (k-input controlled-NOT) gates and implementable by many technologies. The models are extensions of the previously proposed single missing-gate fault (MGF) model, and include multiple and partial MGFs. We study the basic detection requirements of the new fault types and derive bounds on the size of their test sets. We also present optimal test sets computed via integer linear programming for various benchmark circuits. These results indicate that, although the test sets are generally very small, partial MGFs may need significantly larger test sets than single MGFs.

Test data compression has become increasingly popular for distributing test complexity between automatic test equipment and on-chip structures. We provide a general formulation for the code-based test compression problem with fixed-length input blocks and propose a solution approach based on evolutionary algorithms. In contrast to existing code-based methods, we allow unspecified values in matching vectors, which allows encoding of arbitrary test sets using a relatively small number of codewords. Experimental results for both stuck-at and path delay fault test sets for ISCAS circuits demonstrate an improvement compared to existing techniques.

Technology trends are increasing the frequency of serious transient (soft) faults in digital systems. For example, ICs are becoming more susceptible to cosmic radiation, and are being embedded in applications with dynamic noisy environments. We propose a generic framework for representing such faults and characterizing them on-line. We formally define the impact of a transient fault in terms of three basic parameters: frequency, observability and severity. We distinguish fault modes in systems whose noise environment changes dynamically. Based on these ideas, the problem of designing on-line architectures for transient fault characterization is formulated and analyzed for several optimization goals. Finally, experiments are described that determine transient fault impact and the corresponding tests for various simulated fault modes of the ISCAS-89 benchmark circuits.

We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) and a technology-specific part. The first model is based on Shockley equations and is valid for conventional but not deep submicron CMOS. The second model is obtained by fitting SPICE data. The third resistive bridging fault model uses Berkeley predictive technology model and BSIM4; it is valid for CMOS technologies with feature sizes of 90nm and below, accurately describing non-trivial electrical behavior in that technologies. Experimental results for ISCAS circuits show that the test patterns obtained for the Shockley model are still valid for the fitted model, but lead to coverage loss under the predictive model.

Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of reversible elements called k-CNOT (controllable NOT) gates. We review the characteristics of k-CNOT circuits and observe that traditional fault models like the stuck-at model may not accurately represent their faulty behavior or test requirements. A new fault model, the missing gate fault (MGF) model, is proposed to better represent the physical failure modes of quantum technologies. It is shown that MGFs are highly testable, and that all MGFs in an N-gate k-CNOT circuit can be detected with from one to [N/2] test vectors. A design-for-test (DFT) method to make an arbitrary circuit fully testable for MGFs using a single test vector is described. Finally, we present simulation results to determine (near) optimal test sets and DFT configurations for some benchmark circuits.

An ATPG for resistive bridging faults is proposed that combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced so far, it can handle arbitrary non-feedback bridges between two nodes, including ones detectable at higher bridge resistance and undetectable at lower resistance, and faults requiring more than one vector for detection.

We present a technique for making a circuit ready for logic BIST by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.

Test application at reduced power supply voltage (or VLV testing) is a cost-effective way to increase the defect coverage of a test set. Resistive short defects are a major contributor to this coverage increase. Using a probabilistic model of these defects, we quantify the coverage impact of VLV testing for different voltages. When considering the coverage increase, we differentiate between defects missed by the test set at nominal voltage and undetectable defects (flaws) detected by VLV testing. In our analysis, the performance degradation of the device caused by lower power supply voltage is accounted for. Furthermore, we describe a situation in which defects detected by conventional testing are missed by VLV testing and quantify the resulting coverage loss. We report the numbers on the increased defect coverage, flaw coverage, and coverage loss for ISCAS circuits.

We present a simulator for resistive bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look-up, thus exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; reciprocal action of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed and quantitative results with respect to all these definitions are given for the first time.

n-detection test sets for stuck-at faults have been shown to be useful in detecting unmodeled defects. It was also shown that a set of faults, called maximally dominating faults, can play an important role in controlling the increase in the size of an n-detection test set as n is increased. In an earlier work, a superset of the maximally dominating fault set was used. In this work, we propose a method to determine exact sets of maximally dominating faults. We also define a new type of n-detection test sets based on the exact set of maximally dominating faults. We present experimental results to demonstrate the usefulness of this exact set in producing high-quality n-detection test sets.

Verification of designs containing pre-designed cores is a challenging topic in modern IC design. Traditional approaches generally do not use the information that parts of the design (like IP cores) are already verified. In this case, the verification of the IP core reduces to verifying the connectivity between the surrounding design and the core. Therefore, we propose a method that is based on test patterns. Using only those patterns for simulation, in almost all cases 100% of the errors can be detected. Existing test access logic is employed for the application of the patterns. A large set of experimental results is given to demonstrate the efficiency of the approach.

Non-standard fault models often require the application of true-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered.