The Cangyi iron ore belt is a geologically significant sedimentary-metamorphic iron ore belt in China. The transition from open-pit mining to underground mining in the belt is primarily driven by the depletion of surface resources, necessitating the exploration of deep-seated deposits. However, the distribution of these deposits in the Cangyi iron ore belt is intricately controlled by basement fold structures and exhibits late-stage modifications, posing challenges for accurate evaluations of the ore deposits. This study uses a surface magnetic survey to map the planar distribution of the ore bodies. Via 3-D joint inversion of borehole and surface magnetic data, the planar and deep-seated distribution of magnetic iron ore in the belt is obtained. The joint inversion of surface and borehole magnetic data enhances the vertical and horizontal resolutions of deep-seated magnetic sources. This approach is a crucial geophysical method for exploring and characterizing deep mineral resources. Reliance on surface structural traces alone is insufficient for accurate reconstructions of deep structures. Using magnetite inferred from the joint inversion as a marker layer and analyzing the structural trace of the deposit is essential to evaluating the deposit. Previous speculation regarding the presence of a deep-seated ore body at a depth of 1400 m in the exploration area is dispelled by joint inversion of borehole-surface magnetic data, which reveals the absence of highly magnetized magnetic bodies at a depth of 1300 m. This finding provides a clear direction for further deep exploration.

Subcircuit matching in a large-scale analog circuit is a fundamental problem in VLSI computer-aided design (CAD). Existing approaches suffer from a poor scalability issue for a large-scale analog circuit. In this article, we propose a graph learning-boosted subcircuit matching framework for large-scale analog circuits named SMART, consisting of two stages. In the first stage, we customize hypergraph neural networks to map circuit topology for embedding space. Then, coarse subcircuit recognition is directly performed in the embedding space by geometric relations between the query circuit and all candidate subcircuits within the target circuit. In the second stage, a radial matching method, including device attribute matching, connection relationship matching and uniqueness-based matching, is customized to perform fine matching and obtain matches between interconnections and devices in the query circuit and candidate subcircuits. Experimental results show our SMART can outperform state-of-the-art search-based method VF3 and learning-based method NeuroMatch, and achieve the fastest speed. Specifically, using our framework for subcircuit matching can achieve up to$135\times $speedup with slight accuracy loss, and up to$7\times $speedup while maintaining 100% accuracy.

Transistor aging leads to the deterioration of analog circuit performance over time. The worst aging degradation is used to evaluate the circuit reliability. It is extremely expensive to obtain it since several circuit stimuli need to be simulated. The worst degradation collection cost reduction brings an inaccurate training dataset when a machine learning (ML) model is used to fast perform the estimation. Motivated by the fact that there are many similar subcircuits in large-scale analog circuits, in this article we propose Wages to train an ML model on an inaccurate dataset for the worst aging degradation estimation via a domain generalization technique. A sampling-based method on the feature space of the transistor and its neighborhood subcircuit is developed to replace inaccurate labels. A consistent estimation for the worst degradation is enforced to update model parameters. Label updating and model updating are performed alternately to train an ML model on the inaccurate dataset. Experimental results on the very advanced 5 nm technology node show that our Wages can significantly reduce the label collection cost with a negligible estimation error for the worst aging degradations compared to the traditional methods.

Aging degradation dominated by bias temperature instability (BTI) effect is one of the important considerations in system on chip (SOC) design margin. Research on path delay with BTI recovery effect which mitigates degradation is meaningful to set a reasonable aging margin. Since BTI recovery effect known in transistor level occurs very fast, it is a challenge to sample aged path delay in a short interval. In this paper, we propose an aging monitor to investigate the impact of BTI recovery effect on path delay degradation (Δdelay) in nanosecond intervals. The results show that the power function of recovery time accurately fits the trend of Δdelay after the removal of stress. The higher the stress voltage, the faster the absolute value of Δdelay recovers. Increasing stress time obviously reduces the recovery speed of Δdelay. It’s note that BTI recovery effect occurs not only after the removal of stress but also during AC stress. Therefore, the Δdelay is so dependent on stress type that the Δdelay with BTI recovery is 0.2 times of that without BTI recovery. The silicon data also contributes to aging model’s calibration by the introduction of BTI recovery coefficient, which has a ~4% design margin benefit in a 1GHz SOC design.

In advanced technology nodes, power grid metal wires are prone to electromigration (EM) failures due to small wire sizes and high unidirectional current densities. Power grid EM failures usually happen around weak power grid connections delivering current to high power-consuming regions. Previously, power grid EM was mostly addressed at the post-routing stage, which may be too late for a large number of EM violations in modern designs. In this paper, we propose a new set of incremental placement techniques to mitigate power grid EM, including cell move, single row placement, and single tile placement. Experimental results demonstrate the proposed placement techniques can effectively reduce EM violations with negligible wirelength and placement density impacts.