The authors describe a design of an LFSR (linear feedback shift register) that can easily accommodate a change-of-seeds feature. This new LFSR is controlled by two separate clocks, one for the normal LFSR operation and one for the change of seeds option. The change of seeds is fast since it is accomplished by a pair of clock pulses rather than by long scan operations.>

Two test strategies for memory testing are compared for their ability to detect coupled-cell faults in an n-word-by-1-bit random access memory. In both strategies the data-in line is randomly driven. One of the two strategies uses random selection of both the address lines and the read/write control. The other strategy sequentially cycles through the address space with deterministic setting of the read/write control. The relative merit of the two strategies is measured by the average number of accesses per address needed to meet a standard test quality level.>

The authors describe the design of an LSSD-(level-sensitive-scan-design) based LFSR (linear feedback shift register) which is capable of changing seeds by applying a pair of clock pulses at the time of the change. This LFSR is controlled by two separate clocks, one for the normal LFSR operation and one for the change-of-seeds option. The newly generated seeds are uniformly distributed over the entire pattern space. The change of seeds is fast, since it is accomplished by a pair of clock pulses rather than by long scan operations.>

Five test strategies for memory testing are compared for their ability to detect coupled-cell faults in an n-word-by-1-b random-access memory. In all five test strategies the data-in line is randomly driven. Three of five strategies use random selection of both the address lines and the read/write control. The other two strategies sequentially cycle through the address space with deterministic setting of the read/write control. The relative merit of these five strategies is measured by the average number of accesses per address needed to meet a standard test quality level. It is concluded that ETWO (explicit memory test with word operations) offers the best performance and is quite easy to implement.>

A method is presented of operating on signatures from a cycling register such that the complexity of identifying multiple failing tests is comparable to that of identifying a single failing test. The method has some interesting aliasing characteristics. The authors show the probability of aliasing and suggest how it can be kept relatively small. The efficiency of the method decreases as the number of failing tests increase. The reduction in efficiency is due to an increase in aliasing probability caused by footprints being lost in the cycling registers. The larger the number of failing tests, the greater is the chance that aliasing will occur.>

A procedure is described for determining the initial value of a single or multiple input signature register (used to compress responses in built-in testing) so that the final good-machine signature is always constant, e.g. all zeros. In this way, it is possible to determine if a fault has been detected by ORing the outputs of the register stages. Since the OR operation can be built-in, a single observation of the output of the OR gate will determine if the circuit has passed the test.>

In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. Here, the capability of random patterns to detect slow paths in combinational logic is analyzed. Formulas that relate the length of the test to the desired test quality are derived.>

An analytical method is described for determining the random pattern testability of permanent faults in the prelogic driving the data-in and the address lines of a multiport random access memory whose outputs are directly observable. The results can be used with minimal extensions to existing detection probability tools such as the cutting algorithm.

Parallel pseudorandom sequences for use in built-in test are discussed. The two-dimensional nature of these sequences-makes it natural to consider the resulting binary arrays. Some of the desired properties of such arrays are discussed, as well as some of the problems. Generators for such arrays are described. A conventional LFSR with parallel output is shown to be a poor choice for such a generator. Several compact generators are described, which are shown to be compromises between complexity and varying degrees of implementation of the desired properties in the resulting sequences. One of the compact generators produces sequences which have the desired properties for built-in tests.