Previous work on electrothermal simulation using network analysis techniques has been of limited use due to the lack of avalanche breakdown modeling capability and the models to efficiently describe the temperature dynamics. Particularly, simulation of electrical overstress (EOS) and electrostatic discharge (ESD), which are important threats to IC reliability, require an accurate description of temperature-dependent device electrical behaviour including breakdown phenomenon. This paper presents electrothermal device models and their implementation in a new circuit-level electrothermal simulator iETSIM. Simulation results for an I/O protection device in an advanced MOS process are presented to demonstrate iETSIM's ability to accurately model device behaviour up to the onset of second breakdown.>

Numerical algorithms that enable extension of device models into avalanche breakdown region without disturbing the convergence of modified nodal-analysis-based circuit simulators are introduced. Details of model implementation into circuit simulators are presented along with applications. In particular, circuit-level simulation of nondestructive electrostatic discharge phenomena is discussed along with the time-step size on the simulation of negative resistance structures.>

An analytical delay model for BiCMOS driver circuits is presented. The model is based on physical device parameters and can be used to estimate both the pull-up and the pull-down times for a variety of circuit configurations. The intrinsic delay associated with the bipolar transistors is taken into consideration by using a charge control model that incorporates the high-injection effects upon the current gain and the base transport factor. Separate sets of delay equations are derived for the pull-up and pull-down transient responses to account for significant differences between the two cases. The comparison with SPICE circuit simulation results shows that the new model predicts the respective delay times with less than 10% error in most cases. The influence of device dimensions upon the driver delay time is also investigated. The model has been applied to find an optimal area allocation between the CMOS and bipolar parts of the driver circuit when the total available area is limited as in the standard cell configuration.>