This work presents GeST (Generator for Stress-Tests): a framework for automatically generating CPU stress-tests. The framework is based on genetic algorithm search and can be used to maximize different target CPU metrics such as power, temperature, instructions executed per cycle and dl/dt voltage noise. We demonstrate the generality and effectiveness of the framework by generating various workloads that stress the CPU power, thermal and voltage margins more than both conventional benchmarks and manually written stress-tests. The key framework strengths are its extensibility and flexibility. The user can specify custom measurement and fitness functions as well as the CPU instructions that will be used in the genetic algorithm search. The paper demonstrates the framework prowess by using it with simple and complex fitness functions to generate stress-tests: a) for various platform types ranging from low-power mobile ARM CPUs to high-power x86 CPUs and b) with different measurement instruments such as oscilloscopes and software accessible performance counters and sensors.

Power delivery is a well-known challenge for high-end microprocessor systems. Comparatively, mobile computing platforms typically consume order-of-magnitude lower currents, but economic and volume constraints limit the quality of the Power Delivery Network. In addition, the trend towards GHz+ operating frequencies and the ubiquity of low-power techniques such as clock-gating and power-gating, make these systems susceptible to pathological AC transients. Consequently, mobile computing systems are ultimately limited by power-delivery. In this paper, we present the system-level Power Delivery Network (PDN) modeling, analysis and measurement results on a dual-core 64bit ARM Cortex-A57 compute cluster in 28nm CMOS. We present a comprehensive analysis of the PDN by characterizing the individual contribution of each constituent i.e. the PCB, package and the die. We present frequency- and time-domain simulation results and correlate that with measurement (both on-chip and off-chip). Our results demonstrate how complex software and micro-architectural interactions can trigger PDN resonances that ultimately lead to system failure.

Resonant supply voltage noise is emerging as a serious limitation for power efficiency in SoCs for mobile products. Increasing supply currents coupled with stagnant package inductance is leading to significant AC supply impedance, which necessitates increasing supply voltage margins, impacting power efficiency. Adaptive clocking offers a potentially promising approach to reduce voltage margins, by stretching the clock period to match datapath delays. However, the adaptation bandwidth and clock distribution latencies required can be very demanding. We present analysis of the potential benefits from adaptive clocking based on measurements of supply voltage noise in a dual-core ARM Cortex-A57 cluster in a mobile SoC. By modeling an adaptive clocking system on the measured supply voltage noise dataset, we demonstrate that an adaptation latency of 1.5ns may offer a VMINimprovement of around 30mV and at 1ns improvements of 50mV. Benefits are workload dependent and ultimately limited by insurmountable synchronization and clock distribution latency.

In this paper, we present a novel circuit-level timing error mitigation technique, which aims to increase energy-efficiency of digital signal processing datapaths without loss of robustness. Timing errors are detected using razor flip-flops on critical-paths, and the error-rate feedback is used to control a dynamic voltage scaling control loop. In place of conventional razor error correction by replay, we propose a new approach to bound the magnitude of intermittent timing errors at the circuit level. A timing guard-band is created by shaping the path delay distribution such that the critical paths correspond to a group of least-significant bit registers. These end-points are ensured to be critical by modifying the topology of the final stage carry-merge adder, and by using tool-based device sizing. Hence, timing violations lead to weakly correlated logical errors of small magnitude in a mean-squared-error sense. We examine this approach in an finite-impulse response (FIR) filter and a 2-D discrete cosine transform implementation, in 32-nm CMOS. Power saving compared to a conventional design at iso-frequency is 21%-23% at the typical corner, while retaining a voltage guard-band to protect against fast transient changes in switching activity and supply noise. The impact on minimum clock period is small (16%-20%), as it does not necessitate the use of ripple-carry adders and also requires only a bare minimum of additional design effort.

The Razor dynamic voltage scaling approach uses in situ error-detection and correction of timing errors to reclaim safety margins for improved energy-efficiency in digital circuits. In this paper, we propose the use of a time borrowing window on critical logic paths, over which timing errors can resolve safely without an explicit replay mechanism. We demonstrate that time borrowing can be incorporated into DSP pipelines without increasing the minimum clock period, while removing the metastability risk associated with many previously published approaches to replay-free timing error tolerance. A novel hybrid control approach is used to ensure timing violations do not exceed the safe borrowing window. Implementation and back-end simulation of FIR and FFT pipelines demonstrate a significant power reduction. Simulation of the hybrid control loop demonstrates robustness of the proposed approach.

In this paper, we present a novel circuit-level timing error mitigation technique, which aims to increase energy-efficiency when applying a known in situ error-detection and correction technique, called Razor, to DSP datapaths. Timing errors are detected using Razor flip-flops at critical-path endpoints and the error-rate feedback is used to control a dynamic voltage scaling (DVS) control loop. We propose a new approach to bound the magnitude of intermittent timing errors at the circuit level by introducing a guard-band over which timing errors are safely mitigated. The guard-band is achieved by shaping the path delay distribution such that the critical paths correspond to a group of LSB result registers. These end-points are ensured to be critical by modifying the topology of the final stage carry-merge adder and by using tool-based device sizing. Hence, timing violations lead to weakly correlated logical errors of small magnitude in a mean-squared-error sense. We applied this approach to a digital filter in 32nm CMOS. Power saving compared to a conventional design was 23%, over worst-case process and temperature corners.

We propose a novel FIR filter architecture that mitigates sub-critical timing violations as they occur in the pipeline structure by momentarily bypassing affected coefficients. Timing violations are detected using known in situ circuit-level techniques based on late transition detection at timing end points. The approach enables operation with a small but non-zero logical error rate, such that process, voltage and temperature margins can be eliminated without compromising stop-band attenuation. The proposed architecture is implemented in a 90nm CMOS process technology using a typical commercial standard cell implementation flow and verified using full model SPICE simulations. The filter operates at a maximum clock frequency of 420 MHz at 1 V, with an estimated area and power overhead of 26% and 24% respectively compared to a conventional implementation. At the typical process and temperature corner, the proposed architecture can be scaled in voltage down to the point of first failure at 730 mV, thereby achieving a 53% power saving, with no detectable degradation in stop-band attenuation characteristics.

We review adaptive design techniques with particular emphasis on error-tolerant techniques. We compare and contrast traditional adaptive approaches with error-tolerant techniques and analyze the margins eliminated by each of them. We discuss the applications of the latter to on-chip communication and signal-processing. Finally, we focus on a specific example of an error-tolerant technique for general-purpose computing called Razor.

Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-to-market and reduced non-recurring engineering costs, automatic systems that can rapidly generate hardware bearing both power and performance in mind are extremely attractive. This paper proposes the BLADES (Better-than-worst-case Loop Accelerator Design) system for automatically designing self-tuning hardware accelerators that dynamically select their best operating frequency and voltage based on environmental conditions, silicon variation, and input data characteristics. Errors in operation are detected by Razor flip-flops, and recovery is initiated. The architecture efficiently supports detection, rollback, and recovery to provide a highly adaptable and configurable loop accelerator. The overhead of deploying Razor flip-flops is significantly reduced by automatically chaining primitive computation operations together. Results on a range of loop accelerators show average energy savings of 32% gained by voltage scaling below the nominal supply voltage.