An implementation of the IEEE 1149.1 standard, commonly called the JTAG (Joint Test Action Group) standard and created to address the time and cost issues associated with developing digital systems, is presented in this paper. Rules are given for removing gated clocks, registering all the TAP controller outputs, and daisy-chaining the boundary-scan cell clocks, resets, and control signals in a direction opposite to that of TDI to TDO signal. Several major advantages are obtained as a result of these implementation rules. Timing issues that occur while shifting between the boundary cells when the design is in layout are eliminated. During EXTEST instruction execution, skew is introduced between the toggling pad outputs to minimize damaging power spikes. Due to the elimination of the gated clocks, scan can be inserted without additional DFT logic. A method for inserting scan is given which mostly eliminates timing issues during shifting. Since the TAP controller outputs are fully registered and the gated clocks are recommended to be enables, more observe and control locations are available for an ATPG tool to easily create a high fault coverage pattern for the JTAG logic.

It is shown that the TMS pin of IEEE Std. 1149.1 can also be-used for providing stimulus during analog measurements using the architectures of [Park93] and [Lu94]. This results in the saving of one test pin for these architectures. Simulation results show that mixed-signal testing can be safely performed using the new approach without compromising the effectiveness of the approaches of [Park93] and [Lu94].

A structure for testing the interconnect faults and measurement of discrete components on mixed-signal boards is proposed. The structure requires one analog pin in addition to the IEEE 1149.1 pins on each mixed-signal IC. Simulation results are provided to show the accuracy of the metrology.

Describes test quality measures that quantify the completeness of a functional test. The measures are based on exercising a functional model of the unit with the given set of test sequences. Two metrics are proposed: the control-flow coverage (FC1) indicates how completely the logical flow of the functional model is traversed, and the data path coverage (FC2) indicates how completely the data paths have been exercised over a specified set of observable values. The metrics were evaluated using an RTL model of a RISC processor and a combinational circuit.>

Sensitivity analysis is used to diagnose hard faults in analog circuits. Necessary and sufficient conditions are given to determine the suitability of a given parameter for diagnosis. It is also shown that if a parameter is not suitable then a functional variation of the parameter may be used for diagnosis.>

A complete analysis of the bridging faults between gate outputs in FC (full complementary) MOS and PE (precharge evaluate) MOS is presented. It is shown that circuit design to force wired-AND or wired-OR effects in the presence of bridging faults leads to an adverse effect on noise margin, area, and speed. Hence, a functional testing is not desirable if FC MOS gates are employed, and the alternative method involving current testing should be used. In PE MOS gates, however, current testing is not possible, and, therefore, functional testing must be resorted to, despite the adverse side effects. The authors consider an area-efficient implementation of PLAs (programmable logic arrays) which uses both FC MOS and PE MOS logic, an implementation that is commonly used in VLSI designs. All possible classes of bridging faults in this implementation are identified and methods of detecting them are given.>

A built-in self-test (BIST) design method for large embedded CMOS folded programmable logic arrays (PLAs) is presented that is based on a deterministic, function-independent structural method. It requires about half the testing time and comparable area overhead of deterministic BIST methods applied to corresponding nonfolded PLAs. Tests to detect stuck-at, bridging, cross-point and stuck-open faults are given.>

The problem of testing sequential machines using a checking experiment is investigated. An algorithm is given to augment sequential machines by adding extra input(s) to make them testable. We also present a circuit modification method, similar to scan methods, such that the augmented machine can be tested by the checking experiment. A justification of our method for a VLSI environment is given by determining the overheads.

The problem of testing sequential machines using checking experiments is investigated. A method of modifying sequential machines by adding a controllable input is presented. A procedure is given to construct checking experiments for the modified machine and it is shown that only one output observation is sufficient to determine whether the machine is fault free.

The presence of redundancy in combinational networks increases the cardinality of the test set to detect all stuck-at-faults. A solution to this problem is to identify and remove all redundancies in the networks before deriving test sets. It is shown in this paper that the identification of redundancy in arbitrary combinational networks is an extremely tedious problem.

It is shown that the number of maximal false vertices and minimal true vertices is the minimum number of tests required to detect all s-a-1 and s-a-0 faults in any irredundant two-level realization of a 2-monotonic function.