This paper provides an overview on the introduction of electric vehicles (EV) and discusses how electric mobility will influence the developments in automotive industry by integrating the EVs into the Internet of Energy (IoE) and Smart grid infrastructure by providing novel business models and requiring new semiconductor devices and modules. In this context the EVs are evolving from mere transportation mediums to advanced mobile connectivity ecosystem platforms.

Smart systems consist of heterogeneous subsystems and components providing different functionalities; they are normally implemented as Multi-Package on a Board. To fully exploit the potential of current nano-technologies, as well as to enable the integration of existing/new IPs and More than Moore devices, smart system miniaturization and MultiChip in a Package implementation are unavoidable. Furthermore, such goals are only achievable if dedicated M2M interfaces and SW tools for smart subsystems/components design and integration are available to designers and system integrators. This paper offers an overview of the major challenges, as perceived from the industrial point of view, to be faced when pursuing effective smart system design capabilities, discussing and motivating the needs and the market opportunities.

One of the most important challenges facing the entire globe is the trend towards an aging population. By 2045, there will be more people over 60 years old than younger than 15, thus raising from 600mln to 2bln worldwide. This will raise the number of patients with age-specific, chronic and degenerative diseases (e.g. cardio-vascular, cancer, diabetes, Alzheimer's, Parkinson's). Minimally-invasive imaging technologies such as PET (Positron Emission Tomography) and MPI (Magnetic Resonance Imaging) play a vital role in detecting and tracking the evolution of the above mentioned illnesses and determining the strategy and the effectiveness of the prescribed therapies. So far the detection unit of PET equipment has been implemented using photomultipliers tubes (PMTs). A novel solid state photo-detector, the Silicon photomultiplier (SiPM), can replace the PMT, offering, among many other advantages, the possibility of PET/MRI combo equipment.

While transistors per square millimeter and on-chip clock keep scaling smoothly according to Moore’s Law, Vdd does not, nor does Vth. This leads to a dramatic increase in chip power density, and to a significant shift in the balance between dynamic and leakage power. In spite of the recent effort made by EDA vendors in delivering novel solutions that help mitigating the effects on power consumption of technology scaling, the question of whether EDA industry is taking the low-power matter seriously still remains. This session will provide an answer to this intriguing question, by first offering a short review of the state of-the-art in design technologies for dynamic and leakage power minimisation. The session will then continue with a public “trial”, in which OEMs, IDMs, IP and fabless semiconductor vendors will play the role of the public prosecutor, against defendant EDA industry. The court’s ruling will tell us about the future targets the EDA vendors will pursue in low-power design technologies.

Today's system on chip (SoC) technology can achieve unprecedented computing speed that is shifting the IC design bottleneck from computation capacity to communication bandwidth and flexibility. This paper presents an innovative methodology for automatically generating the energy models of a versatile and parametric on-chip communication IP (STBus). Eventually, those models are linked to a standard systemC simulator, running at BCA and TLM abstraction level. To make the system power simulation fast and effective, we enhanced the STBus class library with a new set of power profiling features ("Power API"), allowing to perform power analysis either statically (i.e.: total avg. power) or at simulation runtime (i.e.: dynamic profiling). In addition to random patterns, our methodology has been extensively benchmarked with the high-level systemC simulation of a real world multi-processor platform (MP-ARM). It consists of four ARM7TDMI processors accessing a number of peripheral targets (including several banks of SRAMs, Interrupt's slaves and ROMs) through the STBus communication infrastructure. A remarkable amount of SW layers are executed on top of MP-ARM platform, including a distributed real-time operating system (RTEMS) and a set of multi-tasking DSP applications. The power analysis of the benchmark platform proves to be effective and highly correlated, with an average error of 9% and a RMS of 0.015 mW vs. the reference (i.e. gate level) power figures.

This work focuses on communication architecture analysis for multi-processor systems-on-chips (MPSoCs), and it leverages a SystemC-based platform to simulate a complete multi-processor system at the cycle-accurate and signal-accurate level. These features allow to stimulate the communication sub-system with functional traffic generated by real applications running on top of a configurable number of ARM processors. This opens up the possibility for communication infrastructure exploration and for the investigation of its impact on system performance at the highest level of accuracy. Our simulation environment proved capable of a detailed comparative analysis between two industry-standard communication architectures, under realistic workloads and different system configurations, pointing out the impact of fine grained architectural mismatches on macroscopic performance differences.

Main goal of the paper is introducing a dynamic branch prediction scheme suitable for energy-aware VLIW (Very Long Instruction Word) processors. The proposed technique is based on a compiler hint mechanism to filter the accesses to the branch predictor blocks. Experimental results have been carried out on Lx/ST200, an industrial 4-issue VLIW architecture. We gathered two sets of results: First, by introducing the proposed low-power branch prediction technique in the Lx processor, which features fully static branch prediction, a significant improvement of the energy-delay metric has been observed. Second, we evaluated filtering efficacy of the proposed method and we found that it gets an access reduction to the branch prediction unit of 93% with respect to a processor directly derived from Lx, featuring cycle-by-cycle prediction, corresponding to an average 9% energy reduction of the whole processor power budget.

Main goal of the paper is to introduce a branch prediction scheme suitable for energy-efficient VLIW (Very Long Instruction Word) processors aiming at reducing the energy associated with the prediction phase by filtering the accesses to the branch predictor block. To analyze the effectiveness of the proposed low-power branch prediction scheme, we combined it to some well-known dynamic branch prediction techniques suitable for VLIW processors. Experimental results have been carried out on Lx, a 4-issue VLIW architecture with 6-stage pipeline. The proposed solution implies a performance improvement of 7% on average and an average energy reduction of 15%.

Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power modeling methodology is the key issue to define an effective energy-aware software optimisation strategy for state-of-the-art ILP (Instruction Level Parallelism) processors. The methodology is based on an energy model for VLIW processors that exploits instruction clustering to achieve an efficient and fine grained energy estimation. The approach aims at reducing the complexity of the characterization problem for VLIW processors from exponential, with respect to the number of parallel operations in the same very long instruction, to quadratic, with respect to the number of instruction clusters. Furthermore, the paper proposes a spatial scheduling algorithm based on a low-power reordering of the parallel operations within the same long instruction. Experimental results have been carried out on the Lx processor, a 4-issue VLIW core jointly designed by HPLabs and STMicroelectronics. The results have shown an average error of 1.9% between the cluster-based estimation model and the reference design, with a standard deviation of 5.8%. For the Lx architecture, the spatial instruction scheduling algorithm provides an average energy saving of 12%.

Summary form only given. The overall goal of this work is to define an instruction-level power macro-modeling and characterization methodology for VLIW embedded processor cores. The approach presented in this paper is a major extension of the work previously proposed, targeting an instruction-level energy model to evaluate the energy consumption associated with a program execution on a pipelined VLIW core. Our ongoing work aims at defining a power optimization technique based on the proposed model. The technique consists of a spatial rescheduling of the operations within the same long instruction to reduce their instruction power overhead.

Proposes a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, which provides operands from interstage pipeline registers directly to the inputs of the function units. The power optimization technique exploits the forwarding paths to avoid the power cost of writing/reading short-lived variables to/from the register file (RF). Such optimization is justified by the fact that, in application-specific embedded systems, a significant number of variables are short-lived, that is, their liveness (from first definition to last use) spans only few instructions. Values of short-lived variables can thus be accessed directly through the forwarding registers, avoiding writeback to the RF by the producer instruction and successive read from the RF by the consumer instruction. The decision concerning the enabling of the RF writeback phase is taken at compile time by the compiler static scheduling algorithm. This approach implies a minimal overhead on the complexity of the processor control logic and, thus, no critical path increase. The application of the proposed solution to a VLIW embedded core has shown an average RF power saving of 7.8% with respect to the unoptimized approach on the given set of target benchmarks.

In this paper, a low-power approach to the design of embedded VLIW processor architectures is proposed. To solve the most part of data hazards in the pipeline, processors use forwarding (or bypassing) hardware to provide the required operands from the inter-stage pipeline registers directly to the inputs of the function units. The operands are then stored in the register file during the write-back pipeline stage. In this paper, we propose a power optimization technique based on the exploitation of the forwarding paths in the processor to avoid the power cost of writing/reading short-lived variables to/from the register file. In application-specific embedded systems, experimental evidence has shown that a significant number of variables are short-lived, that is their liveness (front first definition to last use) spans only few instructions. Values of short-lived variables can be accessed directly through the forwarding registers, avoiding write-back. An application example of our solution to a VLIW embedded core, when accessing the register file, has shown a power saving up to 35% with respect to the unoptimized approach on the given set of target benchmarks. The performance overhead is equal to one-gate delay to be added on the processor critical-path.

Article Share on Low-power technology mapping for mixed-swing logic Authors: Rob A. Rutenbar Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PAView Profile , L. Richard Carley Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PAView Profile , Roberto Zafalon STMicroelectronics, Agrate (MI), Italy STMicroelectronics, Agrate (MI), ItalyView Profile , Nicola Dragone Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA and PDF Solutions, Desenzano (BS), Italy Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA and PDF Solutions, Desenzano (BS), ItalyView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 291–294https://doi.org/10.1145/383082.383171Online:06 August 2001Publication History 2citation209DownloadsMetricsTotal Citations2Total Downloads209Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Abstract: In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of abstraction. Only those components that are activated by a given input vector are added to the detailed simulation netlist. The methodology is suitable for parallel implementation on a multi-processor environment and allows to arbitrarily switch between fast and detailed levels of abstraction during the simulation run. The experimental results obtained on a significant set of benchmarks show that it is possible to obtain a considerable reduction in both CPU time and memory occupation together with a considerable degree of accuracy. Furthermore the proposed technique easily fits in the existing industrial design flows.

An automatic modeling technique is presented in this paper that allows to build an accurate model of power consumption in embedded memory blocks. A software neural-network is used to create a regression tree by automatically splitting those variables that have a discontinuous effect on the power consumption. An application of the methodology to the modeling of a 0.35µm CMOS embedded SRAM is presented.

Power dissipation in digital circuits is strongly pattern dependent. Thus, to derive accurate simulation-based power estimates, a large amount of input vectors is usually required. This paper proposes a vector compaction technique aiming at providing accurate power figures in a shorter simulation time for complex sequential circuits characterized by some hundreds of inputs. From pair-wise spatio-temporal signal correlations, the proposed approach is based on bit clustering and temporal partitioning of the input stream aiming at preserving the statistical properties of the original stream and maintaining the typical switching behavior of the circuit. The effectiveness of the proposed approach has been demonstrated over a significant set of industrial case studies implemented in CMOS submicron technology. While achieving a 10x to 50x stream size reduction, the reported results show an average and maximum errors of 2.4% and 7.1% respectively, over the simulation-based power estimates derived from the original input stream.