Color filter array interpolation, also known as demosaicking and “debayering,” is a crucial process for image reconstruction in digital still cameras. This paper presents an edge-oriented demosaicking method and an efficient very-large-scale integration (VLSI) architecture for color interpolation. The design uses simple operations (addition, subtraction, shift, and comparator) and nearest neighboring pixels to catch the color difference and edges. The required line buffering of the proposed design is four lines; therefore, its hardware cost is low. Our extensive experiments revealed that the proposed technique preserved edge features and exhibited excellent quantitative evaluation and visual quality performances. Compared with the previous VLSI implementations, the proposed design achieved superior image qualities. The synthesis results revealed that by using Taiwan Semiconductor Manufacturing Company 0.18-$\mu \text{m}$ technology, the proposed design yields a processing rate of approximately 200M samples per second.

The outage probabilities (OPs) of cognitive amplify‐and‐forward systems with the conventional and the switching‐based partial relay selection (PRS) schemes over independent but not identically distributed Rayleigh fading channels are evaluated. The conventional PRS scheme always depends on the instantaneous channel quality of the first hop, while the switching‐based PRS scheme is based on the estimated average channel state information (CSI) of the first and second hops. For the switching‐based PRS scheme, the instantaneous CSI for links with the smaller average channel power in the first and the second hops for each end‐to‐end path is used for relay selection. Thus, the switching‐based PRS scheme counts on the instantaneous CSI of either the first or second hop. The tight lower bounds and asymptotic expressions of the OP are derived. The feedback overheads of both schemes are discussed. Simulation results substantiate the theoretical analysis and also reveal that the switching‐based PRS outperforms the conventional one over the cognitive relay networks in terms of OP.

In intelligent transportation systems, human detection is an important issue and has been widely used in many applications. Histograms of oriented gradients (HOG) are proven to be able to significantly outperform existing feature sets for human detection. In this paper, we present a low-cost high-speed hardware implementation for HOG feature extraction. The simulation shows that the proposed circuit can achieve 167 MHz with 153-K gate counts by using Taiwan Semiconductor Manufacturing Company 0.13-μm technology. Compared with the previous hardware architectures for HOG feature extraction, our circuit requires fewer hardware costs and achieves faster working speed.

Images are often corrupted by impulse noise in the procedures of image acquisition and transmission. In this paper, we propose an efficient denoising scheme and its VLSI architecture for the removal of random-valued impulse noise. To achieve the goal of low cost, a low-complexity VLSI architecture is proposed. We employ a decision-tree-based impulse noise detector to detect the noisy pixels, and an edge-preserving filter to reconstruct the intensity values of noisy pixels. Furthermore, an adaptive technology is used to enhance the effects of removal of impulse noise. Our extensive experimental results demonstrate that the proposed technique can obtain better performances in terms of both quantitative evaluation and visual quality than the previous lower complexity methods. Moreover, the performance can be comparable to the higher,- complexity methods. The VLSI architecture of our design yields a processing rate of about 200 MHz by using TSMC 0.18 μm technology. Compared with the state-of-the-art techniques, this work can reduce memory storage by more than 99 percent. The design requires only low computational complexity and two line memory buffers. Its hardware cost is low and suitable to be applied to many real-time applications.

In this paper, we present an efficient chip for the removal of impulse noise in images. Our design uses a mask on each pixel in the image to determine whether it is likely being corrupted by random-valued impulse noise or not. After noise detection, we reconstruct the noisy pixel by considering the possible edges existed in the mask and applying a median filter on it. The memory requirement of the proposed method is quite small. The experimental results demonstrate that our method achieves excellent performance in quantitative evaluation and visual quality. An efficient VLSI architecture for this scheme is developed and it yields a processing rate of about 200 MHz by using TSMC 0.18 μm technology.

In this paper, a low-power design of Viterbi decoder is presented. Based on the adaptive Viterbi algorithm, we use a dynamic setting method to set various threshold values for different decoding stages under a particular SNR and efficient reduce the average number of survivor paths. Furthermore, a flexible soft intellectual property core and an auxiliary software system for low-power Viterbi decoder are proposed. In the VLSI realization, we apply the clock-gating technique to disable the activation of registers for nonsurvivor paths. Hence, the power consumption can be reduced. Compared with others, our design requires the lower power consumption for the same SNR condition.

Image and video signals might be corrupted by impulse noise in the process of signal acquisition and transmission. In this paper, an efficient VLSI implementation for removing impulse noise is presented. Our extensive experimental results show that the proposed technique preserves the edge features and obtains excellent performances in terms of quantitative evaluation and visual quality. The design requires only low computational complexity and two line memory buffers. Its hardware cost is quite low. Compared with previous VLSI implementations, our design achieves better image quality with less hardware cost. Synthesis results show that the proposed design yields a processing rate of about 167 M samples/second by using TSMC 0.18 ¿m technology.

In this letter, a novel image restoring technique for interlaced video is presented. We employ a motion-degree detector to determine the type of motion in the adjacent pictures efficiently and a hybrid interpolation based on spatial and/or temporal information to restore the missing pixels for each motion type. Extensive experimental results demonstrate that our method can obtain better performances in terms of both quantitative evaluation and visual quality than the state-of-the-art image restoring techniques. Since the proposed method requires low computational complexity, it is very suitable for real-time hardware implementation and can be applied to current television systems.

Image scaling is a very important technique and has been widely used in many image processing applications. In this paper, we present an edge-oriented area-pixel scaling processor. To achieve the goal of low cost, the area-pixel scaling technique is implemented with a low-complexity VLSI architecture in our design. A simple edge catching technique is adopted to preserve the image edge features effectively so as to achieve better image quality. Compared with the previous low-complexity techniques, our method performs better in terms of both quantitative evaluation and visual quality. The seven-stage VLSI architecture of our image scaling processor contains 10.4-K gate counts and yields a processing rate of about 200 MHz by using TSMC 0.18-mum technology.

In this paper, we present a real-time image denoising chip. For each pixel of the image under processing, our design uses a mask on it to determine whether it is likely being corrupted by impulse noise or not. After the noise detection, we reconstruct the noisy pixel by considering the possible edges existed in the mask. Particularly, our design removes the noise from corrupted images efficiently and requires no previous training. Extensive simulations demonstrate that the proposed method achieves excellent performance in quantitative evaluation and visual quality. Furthermore, the computational complexity of the proposed method is low and its memory requirement is small. An efficient VLSI architecture for this scheme is developed and it yields a processing rate of about 150 MHz by using TSMC 0.18mum technology.

In this letter, a novel algorithm for removing salt-and-pepper noise from corrupted images is presented. We employ an efficient impulse noise detector to detect the noisy pixels, and an edge-preserving filter to reconstruct the intensity values of noisy pixels. Extensive experimental results demonstrate that our method can obtain better performances in terms of both subjective and objective evaluations than those state-of-the-art impulse denoising techniques. Especially, the proposed method can preserve edges very well while removing impulse noise. Since our algorithm is algorithmically simple, it is very suitable to be applied to many real-time applications.