Valerio Vignoli · EDBT 2026 Demo

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Valerio Vignoli

dblp:94/5904 · DBLP profile ↗

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18ranked-venue papers

0as first author

3since 2021 · last 2023

0000-0003-2509-6566ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 18 · 3 since 2021Artificial intelligence and machine learning · 1

Year	Publication	Venue	Position
2023	Multi-Phase Frequency Measurement Exploiting FPGA Mixed-Mode Clock Management for QCM-D Technology abstract We have proposed a digital frequency measurement technique with enhanced accuracy, exploiting FPGA Mixed-Mode Clock Management for QCM-D technology. In detail, the method is based on the multi-phase generalization of the basic direct period measurement technique, involving low-complexity digital architectures based on gated counters. Theoretical analysis has been validated by experimental results, referring to a design implemented on a Xilinx Artix-7 FPGA. The proposed solution allowed to reach a worst-case frequency measurement error of ≈ 20Hz for an observation period of$200\mu \mathrm{s}$of a damped QCM sensor resonating at 10MHz. Tommaso Addabbo, Ada Fort, Riccardo Moretti, Filippo Spinelli, Valerio Vignoli	ISCAS	5
2022	A Low-Complexity Method to Address Process Variability in True Random Number Generators based on Digital Nonlinear Oscillators abstract We discuss a monitoring system aiming to select, among a set of integrated entropy sources affected by process variability, the source guarantying the highest worst-case entropy. The approach is particularly suitable when considering True Random Number Generators based on Digital Nonlinear Oscillators, since multiple instances of the entropy sources can be implemented at a reduced hardware cost. In general, the approach can be applied for TRNGs based on parametric systems, thus offering entropy tuning capabilities. The original theoretical results have been validated with experiments. Tommaso Addabbo, Ada Fort, Marco Mugnaini, Riccardo Moretti, Valerio Vignoli, Duccio Papini	ISCAS	5
2022	A Stochastic Algorithm to Design Min-Entropy Tuning Controllers for True Random Number Generators abstract We discuss a stochastic algorithm to design tuning controllers for cryptographic True Random Number Generators, compliant to NIST recommendations, as an effective low-complexity solution to counteract entropy variability in integrated architectures implementing tunable entropy sources. Taking as a reference the min-entropy concept, we discussed the proposal from both the theoretical and hardware design points of view, validating claims with proofs and experiments. Depending on the target accuracy, the proposed architecture is scalable, and its profitable use in TRNG design strongly depends on the kind of core entropy sources taken into account. Furthermore, we show that the low-complexity entropy measurement techniques exploited in this proposal can be used to design a legitimate alternative to the Adaptive Proportion Health Test recommended in the NIST 800.90B publication. Tommaso Addabbo, Ada Fort, Riccardo Moretti, Marco Mugnaini, Duccio Papini, Valerio Vignoli	IEEE Trans. Circuits Syst. I Regul. Pap.	6
2020	Chaos in Fully Digital Circuits: A Novel Approach to the Design of Entropy Sources abstract We propose a novel class of Digital Nonlinear Oscillators (DNOs) supporting complex dynamics, including chaos, suitable for the definition of high-performance and low-complexity entropy sources in digital programmable devices. We derive our solution from the analysis of simplified models, proposing a low-complexity `fully digital' chaotic entropy source consuming few look-up tables in a Xilinx FPGA. The validity of the proposal has been verified with experiments. Tommaso Addabbo, Ada Fort, Riccardo Moretti, Marco Mugnaini, Hadis Takaloo, Valerio Vignoli	ISCAS	6
2019	Lightweight True Random Bit Generators in PLDs: Figures of Merit and Performance Comparison abstract We investigate and compare three low complexity circuit topologies to be implemented in programmable logic devices, for the design of True Random Bit Generators for Lightweight Cryptography. The architectures, based on the general idea of Digital Nonlinear Oscillators (DNOs), have been compared on the basis of measurement campaigns, carried out referring to figures of merit specifically introduced to assess the quality and reliability of the oscillators under test. Tommaso Addabbo, Ada Fort, Riccardo Moretti, Marco Mugnaini, Valerio Vignoli, Miguel Garcia-Bosque	ISCAS	5
2019	Piecewise Linear Chaotic Maps in Current Mode CMOS Circuits: Nonlinear Distortion Analysis abstract This paper considers the current mode CMOS circuit implementation of the Sawtooth Piecewise Linear chaotic map. Starting from circuit analysis, we discuss a theoretical model to investigate the effects on the dynamical system entropy caused by the map shape nonlinear distortion, introduced by the circuit implementation. The results offer the designer an investigation tool to properly manage some relevant trade-offs related to the CMOS circuit design, highlighting the most critical model parameters affecting the deterioration of the achievable system entropy. Tommaso Addabbo, Ada Fort, Marco Mugnaini, Hadis Takaloo, Valerio Vignoli, Nicola Petra	ISCAS	5
2019	A CMOS PUF Circuit Primitive Based on a Two-Dimensional Nonlinear Dynamical System abstract Adopting a nonlinear dynamical system analysis point of view, we discuss the design of a low-complexity CMOS electronic circuit implementing a Physically Unclonable Function core module based on a two-neurons Cellular Neural Network. The study follows a theoretical approach investigating the circuit topology, aiming at proposing a methodological engineering approach for the design of this class of systems. Tommaso Addabbo, Mauro Di Marco, Ada Fort, Marco Mugnaini, Hadis Takaloo, Valerio Vignoli	ISCAS	6
2019	Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory abstract I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades[1](seeFig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown inFig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade[2],[3]. At the same time, the energy per task has been decreasing at 10–100 X/decade, as shown inFig. 2, for several systems and system-on-chip subsystems[4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit[5]. Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Peter Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim M. Elfadel, Ruonan Han 0001, Masanori Hashimoto, Chun-Huat Heng, Deuk Hyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Li 0001, Huawei Li 0001, Prabhat Mishra 0001, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul Chandra Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta 0003, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu 0001, Wei Zhang 0012, Zhengya Zhang, Jun Zhou 0017, Mark Zwolinski, Stacey Weber	IEEE Trans. Very Large Scale Integr. Syst.	50
2018	Digital Nonlinear Oscillators in PLDs: Pitfalls and Open Perspectives for a Novel Class of True Random Number Generators abstract In this brief we outline a novel perspective for the design of True Random Number Generators in Programmable Logic Devices (PLDs), proposing to bring together PLD design, circuit modeling and the analysis of nonlinear dynamical systems. Although the discussion and experimental results provided in this work refer to FPGA design, the reasoning and concepts have general validity, being easily adaptable to other kind of PLDs, e.g., Complex PLDs (CPLDs). We introduce a novel class of systems, that have been generically named Digital Nonlinear Oscillators, exhibiting complex periodic dynamical behavior, proposing topologies based on Ring Oscillators embedded in looped structures using digital delay blocks and XOR gates. We compared the proposed systems with other solutions proposed in literature, discussing the circuit operation and its nonlinear dynamical behavior. Tommaso Addabbo, Ada Fort, Marco Mugnaini, Valerio Vignoli, Miguel Garcia-Bosque	ISCAS	4
2018	Turbomachinery Clearance Monitoring Based on Passive Variable Reluctance Magnetic Sensors abstract We discuss a novel measurement system based on passive Variable Reluctance Magnetic Sensors (VRSs) to provide clearance measurement for turbo-machine monitoring. The advantage of the solution is in its reliability and low-complexity (in terms of sensor structure, costs and electronic front-end), against an acceptable measurement accuracy, making the proposed method suitable for the condition monitoring of huge turbo-machines requiring a large number of sensors. Tommaso Addabbo, Mauro Di Marco, Ada Fort, Elia Landi, Marco Mugnaini, Valerio Vignoli, Gianluca Ferretti	ISCAS	6
2013	A 1-bit Physically Unclonable Function based on a two-neurons CNN abstract We propose to exploit a two-neurons Cellular Neural Network (CNN) to design a basic 1-bit Physically Unclonable Function (PUF). The analysis discussed in this work, derived from the general theory of CNNs, has been validated by experimental results. Tommaso Addabbo, Ada Fort, Mauro Di Marco, Luca Pancioni, Valerio Vignoli	ISCAS	5
2011	Pseudo-chaotic lossy compression of TRBGs abstract We propose a compression method for True Random Bit Generators (TRBGs) that exploits pseudo-chaotic systems. The compression scheme requires extremely low-complex hardware circuits for being implemented whereas its theoretical explanation is based on a weaker and more general interpretation of the Shadowing Theory, focusing on probability measures, rather than on single chaotic trajectories. We prove theoretically how to design the overall compression scheme, in order to assure the final entropy of the compressed TRBG to be arbitrarily close to the maximum theoretical limit of 1 bit/time-step. Tommaso Addabbo, Ada Fort, Ljupco Kocarev, Santina Rocchi, Valerio Vignoli	ISCAS	5
2008	An efficient and accurate method for computing the invariant measure of piecewise affine chaotic maps abstract In this paper an efficient and accurate method for computing the invariant measure of piecewise affine chaotic maps is proposed. As an application example, the method is used to evaluate for a chaos-based true random bit generator the robustness of the entropy with respect to small map parameters variations. Tommaso Addabbo, Ada Fort, Santina Rocchi, Valerio Vignoli	ISCAS	4
2007	Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map abstract In this paper a novel family of maximum-period nonlinear congruential generators (NLCGs) based on the digitized sawtooth map is considered for the definition of hardware and software efficient pseudo random number generators (PRNGs). A list of such maximum period NLCGs for period lengths up to 231-1 is provided. Referring to the NIST800-22 statistical test suite, a PRNG example based on the combination of two of the proposed NLCGs is presented and discussed Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli	ISCAS	5
2007	Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks abstract In this paper, techniques to improve the resistance against differential power analysis (DPA) attacks of precharged busses in cryptographic circuits are discussed. In particular, two techniques that were previously introduced by the same authors are properly mixed to further enhance the immunity to DPA attacks. The achieved robustness against DPA attacks is shown to be considerably improved, compared with the case of a separate adoption of each technique. Criteria to manage the security-power-area trade-off are also derived from a statistical analysis of precharged busses. The mixed technique is finally validated by means of both cycle-accurate and circuit simulations on the DES encryption algorithm running on a MIPS32 architecture. Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli	ISCAS	4
2006	A technique to design high entropy chaos-based true random bit generators abstract In this paper the theoretical bases to design a true random bit generator (TRBG) circuit with a predefined minimum entropy are discussed. The approach is tailored to TRBGs based on a one-dimensional piecewise-linear chaotic map, and it is based on a feedback control procedure that allows to dynamically changing the system parameters. For this purpose, the procedure just exploits the TRBG output observation without requiring bit throughput reduction. The design approach was validated by an hardware prototype implemented on a field programmable analog array (FPAA) Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli	ISCAS	5
2006	Analysis and design of MCML gates with hysteresis abstract In this paper, hysteresis is exploited to improve the performance of positive feedback source coupled logic circuits, which are a modification of the traditional MOS current-mode logic (MCML) (Alioto, 2004). To understand the effect of hysteresis on the DC characteristics, a model of the noise margin is analytically derived. This model shows that hysteresis improves the noise margin, whose increase is traded-off to reduce the logic swing, which in turn can have a beneficial impact on the speed performance. Practical cases where hysteresis is advantageous are identified, and a comparison with PFSCL gates without hysteresis is carried out. Analysis shows that in such cases hysteresis significantly improves the speed performance and the power efficiency of PFSCL gates, which is a critical aspect in this kind of logic. Simulation results are presented based on a 0.18-mum CMOS process Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli	ISCAS	4
1995	Multielement Ultrasonic System for Robotic Navigation abstract In this paper an ultrasonic multisensor acquisition and processing system with up to 32 air-ultrasound transducers in the frequency range of 40-200 kHz is presented. The system was developed for an obstacle avoidance applications in the robotics field. The acquisition and processing capability of the equipment (based on the digital signal processor TMS320C25 and can sample up to five parallel channels) allows the robot to perform tasks of different difficulty levels, from target-ranging to pattern recognition. As an example of application, a neural approach to a typical problem in the robotic navigation field is presented, which highlights the system-flexibility features. Valerio Gabbani, Santina Rocchi, Valerio Vignoli	ICRA	3