In this paper, we study two different ON-chip power delivery schemes, namely, fully integrated voltage regulator (FIVR) and low-dropout regulator (LDO), and analyze their effect on total system power under process variation, assuming a realistic dynamic voltage-frequency scaling (DVFS) system. The impact of different task scheduling algorithms on the overall system power was also analyzed. We find that in a hypothetical 256-core processor, under a per-core DVFS assumption, the FIVR-based power delivery consumes 20% less power than the LDO-based one for a 50% throughput. However, as the number of cores in the processor reduces, the difference in power consumption between the FIVR-based and LDO-based power delivery schemes becomes smaller. For example, in the case of a 16-core processor with per-core DVFS capability, FIVR-based design was found to consume about the same power as the LDO-based design.

Spin-transfer torque magnetic RAM (STT MRAM) has emerged as a promising candidate for on-chip memory in future computing platforms. We present a cross-layer (device-circuit-architecture) approach to energy-efficient cache design using STT MRAM. At the device and circuit levels, we consider different genres of MTJs and bitcells, and evaluate their impact on the area, energy and performance of caches. In addition, we propose micro-architectural techniques viz. sequential cache read and partial cache line update, which exploit the non-volatility of STT MRAM to further improve energy efficiency of STT MRAM caches. A detailed comparison of STT MRAM caches with SRAM-based caches is also presented. Our results indicate that the proposed optimizations significantly enhance the efficiency of STT MRAM for designing lower level caches.

We present a layout-aware optimization methodology for spin-transfer torque (STT) MRAMs, considering the dependence of cell area on the access transistor width (WFET), number of fingers in the access transistor and the metal pitch of bit- and source-lines. It is shown that for WFETless than a critical value (~7 times the minimum feature length), one-finger transistor yields minimum cell area. For large WFET, minimum cell area is achieved with a two-finger transistor. We also show that for a range of WFET, the cell area is limited by the metal pitch of bit- and source-lines. As a result, in the metal pitch limited (MPL) region, WFETcan be increased with no change in the cell area. We analyze the impact of increase in WFETin the MPL region on the write margin and cell tunneling magneto-resistance (CTMR) of different genres of STT MRAMs. We consider conventional STT MRAM cells in the standard and reverse-connected configurations and STT MRAMs with tilted magnetic anisotropy for the analysis. By increasing WFETfrom the minimum to the maximum value in the MPL region (at iso-cell area) and reducing read voltage to achieve iso-read disturb margin, 2X improvement in write margin and 27% improvement in CTMR is achieved for the reverse-connected STT MRAM. Similar trends are observed for other STT MRAM cells.

Spin transfer torque magnetic random access memory (STT MRAM) is a promising non-volatile memory due to its outstanding potential for high integration density and excellent scalability. Despite the attractive features, high write current and power is still a major challenge. As a result, the optimization of the memory for write is critical.

Radiation-induced soft error rate (SER) degrades the reliability of static random access memory (SRAM)-based field programmable gate arrays (FPGAs). This paper presents a new built-in 2-D Hamming product code (2-D HPC) scheme to provide reliable operation of SRAM-based FPGAs in hostile operating environments such as space. Multibit error correction capability of our built-in 2-D HPC can improve the reliability, and hence, system availability, by orders of magnitude. Simulation results show that the large number of error correction capability of 2-D HPC can recover configuration bits without depending on an external memory preserving a golden copy of the configuration bits. To provide efficient 2-D HPC in a built-in logic, we also propose a new 2-D SRAM buffer. Using the proposed multibit error correction scheme, system availability of an SRAM-based FPGA can be more than 99.9999999% with SRAM cell failures in 1 billion h of operation of 7.

Micro-scale energy harvesting has become an increasingly viable and promising option for powering ultra-low power systems. A power converter is a key component in micro-scale energy harvesting systems. Various design parameters of the power converter, most notably the number of stages in a multi-stage power converter, play a crucial role in determining the amount of electrical power that can be extracted from a micro-scale energy transducer such as a miniature solar cell. Existing stage number optimization techniques for switched capacitor power converters, when used for energy harvesting systems, result in a substantial degradation in the amount of harvested electrical power. To address this problem, this paper proposes a new stage number optimization technique for switched capacitor power converters that maximizes the net harvested power in micro-scale energy harvesting systems. The proposed technique is based on a new figure-of-merit that is well suited for energy-harvesting systems. We have validated the proposed technique through circuit simulations using IBM 65nm technology. Our simulation results demonstrate that the proposed stage number optimization technique results in an increase of 60%-290% in net harvested power, compared to existing stage number optimization techniques.

This paper presents memory-based embedded digital ATE (Automatic Test Equipment) - a new logic BIST methodology that can deliver deterministic test stimuli and stores output responses on a chip. The proposed scheme consists of test data compression logic and a new on-chip SRAM structure, which is operated as a ROM when the logic BIST mode is on. The new BIST-oriented RAM (BRAM) implements ROM features in the BIST mode and incurs no performance penalty in the normal SRAM mode of operation. BRAM can be designed by inserting an additional word line in a row to a conventional SRAM bit-cell (no increase in bit-cell area). BRAM stores the compressed test vectors that can be transmitted to on-chip decompressors during test mode. BRAM also accepts compacted output responses. Experimental results show that BRAM performs stable and high-performance ROM operations in the BIST mode. Run-length coding can be incorporated into the proposed test data compression to reduce test data volume further. Test data volume and fault coverage on ISCAS89 benchmark show that the proposed test methodology can be used as a stand-alone BIST scheme while providing test quality of deterministic tests.

Energy harvesting has emerged as a feasible and attractive option to improve battery lifetime in micro-scale electronic systems such as biomedical implants and wireless sensor nodes. A key challenge in designing micro-scale energy harvesting systems is that miniature energy transducers (e.g., photovoltaic cells, thermo-electric generators, and fuel cells) output very low voltages (0-0.4V). Therefore, a fully on-chip power converter (usually based on a charge pump) is used to boost the output voltage of the energy transducer and transfer charge into an energy buffer for storage. However, the charge transfer capability of widely used linear charge pump based power converters degrades when used with ultra-low voltage energy transducers. This paper presents the design of a new tree topology charge pump that has a reduced charge sharing time, leading to an improved charge transfer capability. The proposed design has been implemented using 65nm technology and circuit simulations demonstrate that the proposed design results in an increase of up to 30% in harvested power compared to existing linear charge pumps.

Thermal energy harvesting using micro-scale thermoelectric generators is a promising approach to alleviate the power supply challenge in ultra low power systems. In thermal energy harvesting systems, energy is extracted from the transducer using an interface circuitry, which plays a key role in the determining the energy extraction efficiency. This paper presents techniques for the systematic modeling, analysis, and design of interface circuitry used in micro-scale thermoelectric energy harvesting systems. We characterize the electrical behavior of a micro-scale thermoelectric transducer connected to a step-up charge pump based power converter and model the relationship between the transducer output voltage and the charge pump switching frequency. We model various power loss components inside the interface circuitry and present an analytical design methodology that estimates optimal parameter values for the interface circuitry. These parameter values lead to maximum net output power being delivered to the energy buffer. We have implemented various interface circuitries using IBM 65nm technology to verify our proposed models and methodology. Circuit simulation results show that the proposed methodology accurately estimates the maximum power point voltage of the system with an error of 3%.

Performance variability in digital integrated circuits can largely affect parametric yield and product reliability in ultra deep submicrometer technologies. As a result, variation resilience is becoming an essential design requirement for future technology nodes, especially for timing critical applications. This paper proposes an on-chip variability sensor using phase-locked loop (PLL) to detect process, supply voltage (VDD), and temperature variations (process, voltage, and temperature variation) or even temporal reliability degradation stemming from negative bias temperature instability. Our analysis shows that control voltage (Vcnt) of voltage-controlled oscillator in PLL can be used as a dynamic performance signature of an operating IC. Along with the proposed PLL-based sensor circuit, we also propose a variation-resilient system technique using adaptive body biasing (ABB). The PLLVcntsignal is efficiently transformed to an optimal body bias signal for various circuit blocks to avoid possible timing failures. Correspondingly, circuits can be designed with significantly relaxed timing constraint compared to conventional approaches, where a large amount of design resources can be wasted to take care of the worst-case situations. We demonstrated our approach on a test chip fabricated in IBM 130-nm CMOS technology. Measurement results show that the PLL-based sensor is cable of tracking various sources of circuit variations. Optimization analysis shows that 42% and 43% reduction in area and power can be obtained using our approach compared to the worst-case sizing. The proposed study refers to our previous study introduced in with major improvements in measurement results and analysis.

This paper evaluates the severity of negative bias temperature instability (NBTI) degradation in two major circuit applications: random logic and memory array. For improved lifetime stability, we propose/select an efficient reliability-aware circuit design methodologies. Simulation results obtained from 65nm PTM node shows that NBTI induced degradation in random logic is considerably lower than that of a single transistor. As a result, simple delay guard-banding can efficiently mitigate the impact of NBTI in random logic. On the other hand, NBTI degradation in memory shows much severe effect especially when combined with the impact of random process variation, NBTI can dramatically reduce the READ stability of memory cells. Hence, aggressive design techniques such as stand-by VDD scaling or adaptive body biasing (ABB) are required in memory application to minimize the impact of NBTI.

In this work, we propose a Schmitt Trigger (ST) based differential sensing SRAM bitcell that can operate at ultra-low supply voltage. The proposed Schmitt Trigger SRAM cell addresses the fundamental conflicting design requirement of read versus write operation of a conventional 6T cell. Schmitt Trigger operation gives better read-stability and as well as better writeability compared to the standard 6T cell. The proposed ST bitcell incorporates a built-in feedback mechanism, achieving process variation tolerance - a must for future nano-scaled technology nodes. Measurements on 10 test-chips fabricated in 130nm technology show that the proposed Schmitt Trigger bitcell gives 58% higher read Static Noise Margin (SNM), 2X higher writetrip-point and 120mV lower read Vmin compared to the conventional 6T cell. The ST SRAM array is operational at 150mV of supply voltage.

Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability concerns in sub- 100nm technologies. So far, studies of NBTI and its impact on circuit performance have assumed an average behavior of the degradation process. However, in very short channel devices, finite number of Si-H bonds in the channel can induce a statistical random variation of the degradation process. This results in significant random Vtvariations in PMOS transistor. The NBTI induced variation depends on operating temperature and the effective stress period for the specific device. In this paper, we analyze the impact of stochastic temporal NBTI variations and propose a compact circuit level Vtmodel. Using the proposed model, we show how temporal Vtvariations can affect the lifetime performance of different circuit topologies including 6T SRAM cell and random combinational logic circuits.