This paper presents a field programmable gate array (FPGA) implementation for a competitive Hopfield neural network (CHNN) to be used in image histogram equalization (HE). This algorithm is so computationally expensive that a viable hardware implementation is appealing provided that an efficient algorithm-to-architecture mapping can be achieved. The Xilinx Virtex-E was used for the hardware realization. An efficient use of the chip is outlined in the results.

This paper presents an FPGA implementation for the Block Truncation Coding (BTC) image compression technique. Images are divided into equal blocks. The BTC calculates the mean of each block for which a two-level quantization is performed so that a zero value is stored for the pixels with values smaller than the mean. The rest of the pixels are represented by the value one. The implementation exploits the inherent parallelism of the algorithm to provide efficient algorithm-to-architecture mapping. FPGA implementation of the BTC is composed of three modules: the input module, to receive input pixels; the quantizer module, to classify pixels to one of the two levels;= and divider circuits to obtain the two quantized values. The implementation is performed for gray and color images. The Xilinx-VirtexE BTC implementation has shown to provide about 23.4x10 6 of pixels/second processing rate which is about 3500 times faster than an Intel Pentium III-550-MHz processor.