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Fernando A. Morales

dblp:94/6350 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Internet architecture and protocols · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Internet architecture and protocols › link-layer protocols
logical link control		 0.011994
Design of a Header Processor for the PSi Implementation of the Logical Link Control Protocol in LANs · HPDC 1994
Internet architecture and protocols › protocol implementation
protocol processing		 0.011994
Design of a Header Processor for the PSi Implementation of the Logical Link Control Protocol in LANs · HPDC 1994
Processor architecture and microarchitecture › instruction set architecture › RISC
RISC processor		 0.011994
Design of a Header Processor for the PSi Implementation of the Logical Link Control Protocol in LANs · HPDC 1994
Internet architecture and protocols › link-layer protocols
IEEE 802.2		 0.011994
Design of a Header Processor for the PSi Implementation of the Logical Link Control Protocol in LANs · HPDC 1994
Internet architecture and protocols › link-layer protocols
local area network protocol		 0.011994
Design of a Header Processor for the PSi Implementation of the Logical Link Control Protocol in LANs · HPDC 1994

Methods — techniques the papers use, named apart from their topics

microprogramming · 0.0RISC architecture · 0.0
YearPublicationVenuePosition
1994 Design of a Header Processor for the PSi Implementation of the Logical Link Control Protocol in LANs
abstract
Fiber optic communications offer a combination of high bandwidth, low error probability, and gigabit transmission capacity. To take advantage of the data transmission rates offered by a fiber optic transmission medium, it is essential to have network processing components that can cope with these rates. One approach to removing the protocol processing bottleneck present in network layers is the PSi architecture. PSi consists of header, connection, and output processors. In this paper, we design a RISC architecture for the PSi header processor. The architecture consists of a two stage pipeline microprogrammed processor with a clock frequency of 50 Megahertz and a throughput of one million packets per second. The specific protocol for which this processor was microprogrammed is the Logical Link Control IEEE 802.2 protocol for LANs.>
Fernando A. Morales, Hosame Abu-Amara
 HPDC1