Cardiopulmonary function and power as well as efficient motion skill are extremely important for athletes. Thanks to the latest sensing technology and smart devices, many researchers have focused on sports-skill analysis. Electromyography (EMG), in particular, is gaining attention as a method of understanding the power-generating process in motions. However, most existing applications using EMG have remained being one-time measurement. This is because athletes do not know how to use the results and how to measure their improvement. We propose a sports-skill-training framework with muscle-usage indicators based on EMG and an EMG live visualization system. With this framework, athletes can determine the skill they need to improve by focusing on skills whose indicators are poor, activate their muscles with live feedback to overcome weaknesses, and quantitatively measure their improvement as the improvement of the indicators during the activation training. We also verified the effect of coaching in this framework on cycling athletes. The experimental results quantitatively indicate the effectiveness of continuous skill training with our framework.

Any hierarchical matrix (H-matrix) can be transformed to an H-matrix with block low-rank representation (BLR). Although matrix arithmetic with BLR is easier than that with the normal H-matrix, memory usage is increased compared to the normal H-matrix O(N log N). Therefore, BLR has been utilized for complex arithmetic functions of relatively small matrices on a CPU node. In this study, we discuss the efficiency of H-matrices with BLR in simple arithmetic functions, such as H-matrix generation and H-matrix-vector multiplication, in large-scale problems on distributed memory computer systems. We demonstrate how the BLR block size should be defined in such problems and confirm that the complexity of the memory usage of H-matrices with BLR is O(N1.5) when using the appropriate block size. We propose a set of parallel algorithms for H-matrices with BLR. In numerical experiments using electric field analyses, the speed-up of the execution time for the simple arithmetic functions in H-matrices with BLR reaches about 10,000 MPI processes. We confirm that even for simple H-matrix arithmetic, the BLR version is significantly faster than the normal H-matrix version, if a large number of CPU cores are used.

We are now developing a manycore-aware implementation of multiprocessed PIC (particle-in-cell) simulation code with automatic load balancing. A key issue of the implementation is how to exploit the wide SIMD mechanism of manycore processors such as Intel Xeon Phi. Our solution is "particle binning" to rank all particles in a cell (voxel) in a chunk of SOA (structure-of-arrays) type one-dimensional arrays so that "particle-push" and "current-scatter" operations on them are efficiently SIMD-vectorized by our compiler. In addition, our sophisticated binning mechanism performs sorting of particles according to their positions "on-the-fly", efficiently coping with occasional "bin overflow" in a fully multithreaded manner. Our performance evaluation with up to 64 nodes of Cray XC30 and XC40 supercomputers, equipped with Xeon Phi 5120D (Knights Corner) and 7250 (Knights Landing) respectively, not only exhibited good parallel performance, but also proved the effectiveness of our binning mechanism.

This paper covers the multi-threaded parallel processing of a sparse triangular solver for a linear system with a sparse coefficient matrix, focusing on its application to a parallel ICCG solver. We propose algebraic block multi-color ordering, which is an enhanced version of block multi-color ordering for general unstructured analysis. We present blocking and coloring strategies that achieve a high cache hit ratio and fast convergence. Five numerical tests on a shared memory parallel computer verify that the computation time of the proposed method is between 1.7 and 2.6 times faster than that of the conventional multi-color ordering method.

This paper proposes a new method for Particle-in-Cell (PIC) simulations which aims at achieving both good load balancing and scalability so as to be efficiently executed on distributed memory systems. This method, named OhHelp, simply and equally partitions the space domain where charged particles reside and assigns each partitioned subdomain to each computation node for scalable simulation with respect to the size of the domain. Load balancing and thus the scalability in terms of the number of particles are accomplished by making each node help another heavily loaded node which deputes a part of particles in its subdomain and replicated subdomain field data to its helpers. The OhHelp load balancer monitors particle movements through subdomain boundaries to check if the helpand-helpers configuration keeps good load balancing and, when unacceptable imbalance is found, dynamically reconfigures it to regain perfect balancing. The efficiency and scalability of OhHelp are confirmed through our experiment with a production-level full-3D plasma simulator and with uniform and non-uniform particle distributions. As a result, we found 256-core parallel simulations, including an extremely imbalanced setting to pack all the particles in a small region, exert 159-190 speedup compared to sequential execution.

This paper reports our 3.75-year empirical study on power-aware operations of Kyoto University’s supercomputer system. The supercomputer system of 10 TFlops had required about 540 kW on average in its first fiscal year 2004. After that and one-year try-and-error of power efficient operation, we implemented a simple but effective scheduler of jobs and machine powering to improve the perload power efficiency by up to 39% and to save 200 kW and $200,000 electric charge in the fiscal year 2006. The power-aware scheduler tries to minimize the number of active nodes in the system of eleven nodes keeping sufficient computational power for given loads. Thus the power-aware scheduler has not degraded, but has significantly improved, the service quality in terms of the average job-waiting time.

This paper proposes an efficient method to analyze worst case interruption delay (WCID) of a workload running on modern microprocessors using a cycle accurate simulator (CAS). Our method is highly accurate because it simulates all possible cases inserting an interruption just before the retirement of every instruction executed in a workload. It is also (reasonably) efficient because it takes O(N log N) time for a workload with N executed instructions, instead of O(N2) of a straightforward iterative simulation of interrupted executions. The key idea for the efficiency is that a pair of executions with different interruption points has a set of durations in which they behave exactly coherent and thus one of simulations for the durations may be omitted. We implemented this method modifying the SimpleScalar tool set to prove it finds out WCID of workloads with five million executed instructions in reasonable time, less than 30 minutes, which would be 200-300 days by the straightforward method. We also show a parallelization of our method achieves a good speedup, about 7-fold with 8-node PC cluster.

In our research project named "Mega-Scale Computing Based on Low-Power Technology and Workload Modeling", we have been developing a prototype cluster not based on ASIC or FPGA but instead only using commodity technology. Its packaging is extremely compact and dense, and its performance/power ratio is very high. Our previous prototype system named "MegaProto" demonstrated that one cluster unit, which consists of 16 commodity low-power processors, can be successfully implemented on just 1U height chassis and it is capable of up to 2.8 times higher performance/power ratio than ordinary high-performance dual-Xeon 1U server units. We have improved MegaProto by replacing the CPU and enhancing the I/O performance. The new cluster unit named "MegaProto/E" with 16 Transmeta Efficeon processors achieves 32 GFlops of peak performance, which is 2.2-fold greater than that of the original one. The cluster unit is equipped with an independent dual network of Gigabit Ethernet, including dual 24-port switches. The maximum power consumption of the cluster unit is 320 W, which is comparable with that of today's high-end PC servers for high performance clusters. Performance evaluation using NPB kernels and HPL shows that the performance of MegaProto/E exceeds that of a dual-Xeon server in all the benchmarks, and its performance ratio ranges from 1.3 to 3.7. These results reveal that our solution of implementing a number of ultra low-power processors in compact packaging is an excellent way to achieve extremely high performance in applications with a certain degree of parallelism. We are now building a multi-unit cluster with 128 CPUs (8 units) to prove that this advantage still holds with higher scalability

In recent years, the use of cache memory has been desired in hard real-time systems in order to reduce the memory access time. To enable it, accurate analysis of the worst-case execution time considering cache flushes is necessary since the cache may be flushed by preempting tasks in a multitask environment. This paper proposes a method to find the worst-case timing of cache flushes and demonstrates its effectiveness.

In our research project "Mega-Scale Computing Based on Low-Power Technology and Workload Modeling", we claim that a million-scale parallel system could be built with densely mounted low-power commodity processors. "MegaProto" is a proof-of-concept low-power and highperformance cluster build only with commodity components to implement this claim. A one-rack system is composed of 32 motherboard "cluster units" of 1 U-height and commodity switches to interconnect them mutually as well as with other racks. Each cluster unit houses 16 low-power dollarbill- sized commodity PC-architecture daughterboards, together with a high bandwidth, 2 Gbps per processor embedded switched network based on Gigabit Ethernet. The peak performance of a one-rack system is 0.48 TFlops for the first version and will improve to 1.02 TFlops in the second version through a processor/daughterboard upgrade. The system consumes about 10 kW or less per rack, resulting in 100 MFlops/W power efficiency with a power-aware intrarack network of 32 Gbps bisection bandwidth, while additional 2.4 kW will boost this to sufficiently large 256 Gbps. Performance studies show that even the first version significantly outperforms a conventional high-end 1U server comprised of dual power-hungry processors in a majority of NPB programs. It is also investigated how the current automated DVS control could save power for the HPC parallel programs along with its limitation.

In order to reduce the overhead of synchronizing operations of shared memory multiprocessors, this paper proposes a mechanism, named specMEM, to execute memory accesses following a synchronizing operation speculatively before the completion of the synchronization is confirmed. A unique feature of our mechanism is that the detection of speculation failure and the restoration of computational state on the failure are implemented by a small extension of coherent cache. It is also remarkable that operations for speculation on its success and failure are performed in a constant time for each independent of the number of speculative accesses. This is realized by implementing a part of cache tag for cache line state with a simple functional memory. This paper also describes an evaluation result of specMEM applied to barrier synchronization. Performance data was obtained by simulation running benchmark programs in SPLASH-2. We found that the execution time of LU decomposition, in which the length of period between a pair of barriers significantly varies because of the fluctuation of computational load, is improved by 13%.

In thk paper a new parallel global and detailed wire routing algorithm called "Amen" is introduced.Both of them are done in parallel using different processor elements (PEs).We introduce a new way of dividing the multilayer grid into layers, and dividing layers into slices.Each PE, in the detailed routing, has a responsibility for one or more slice.This way of division obtains a high degree of parallelism.A new detailed routing algorithm which routes nets under the condition that these net paths do not prevent other nets from being routed later is also introduced.Amen gives high routing quality by using fewer vias and shorter wire length than the other algorithms.The results show that this algorithm obtains higher connection ratio than maze running algorithm.

A system concept of a common alternative routing system is proposed for reducing total network costs by integrating satellite communications into public-switched networks, where satellite systems carry overflow traffic from terrestrial systems through common satellite channels. This concept has been realized by a satellite communication system called DYANET (dynamic channel assigning and routing satellite aided digital networks), which provides trunk circuits in combination with terrestrial systems. The key technologies developed for DYANET are a centralized network control system and a transponder hopping demand assignment TDMA (time-division multiple-access) system, to assure single-hop connection and to use satellite channel efficiently. The authors describe the system concept and configuration, the network control system, and the results of its commercial use.>

The architecture of a pipelined microprocessor for logic programming languages is presented. The microprocessor, called PU (processing unit), is also used as a key component of AI workstations. PU has the capability to execute two different logic programming languages, KL1 for PIM/m and ESP for the AI workstation. The microprocessor has very high performance, 833 KLIPS in KL1 append and 1282 KLIPS in ESP, owing to the pipelined data typing and dereference. For efficient implementation of both languages, data typing and dereference are important. For these operations, PU has mechanisms to manipulate tagged data. The hardware architecture of PU is described, focusing on its data typing and dereference mechanisms.>

We evaluated a Prolog machine PSI (Personal Sequential Inference machine) for the purpose of improving and redesigning it. In this evaluation, we measured the execution speed and the dynamic characteristics of cache memory, register file, and branching hardware introduced for high-speed execution of Prolog programs.Execution speed of the PSI firmware interpreter was found to be comparable to that of the DEC-10 Prolog compiled code on the DEC-2060. It was also found that PSI was faster than DEC for executing programs containing much unification and backtracking that require runtime processing.With the cache memory, the hit ratio for application programs was found higher than 96%; this demonstrates that the Prolog execution has much memory access locality. The memory access frequency and the appearance ratio between Read and Write command were also investigated.Concerning the register file, use rate of each dedicated access mode was measured and effect of each mode was discussed. In the branching function we confirmed a high appearance rate of conditional branches and multi-way branches based on tag values.