A fully integrated, ultra low-power, varying pulse width second-order derivative Gaussian pulse generator designed and fabricated in a commercial 0.18μm CMOS technology is reported for 3-10GHz ultra wideband (UWB) transceivers. The second-order derivative Gaussian pulse generator circuit consists of three cascaded stages for generating square wave, Gaussian impulse, and second-order derivation sequentially. This CMOS second-order derivative Gaussian pulse generator can generate UWB pulses with adjustable pulse width ranging from 220 picoseconds to a few nanoseconds. Measured circuit performance achieves a very short pulse width of <1ns, an amplitude of 70mV and an ultra low power consumption of 2mW at 100MHz pulse repeating frequency. The pulse generator fully complies with FCC power mask.

On-chip ESD (electrostatic discharging) protection is a challenging IC design problem. New CAD tools are essential to ESD protection design prediction and verification at the full chip level. This paper reports a new CAD tool, entitled ESDZapper, to simulate the complex ESD protection zapping test, procedures and to find the critical discharging path under a specific ESD stress. ESDZapper is developed based on a novel concept of ESD-critical parameters. Capability of the new tool is demonstrated using a practical design example in a 0.35μm BiCMOS technology.

On-chip electrostatic discharge (ESD) protection design is a challenging IC design problem. New computer-aided design (CAD) tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel smart parametric-checking mechanism and a new intelligent CAD tool, entitled ESD inspector, developed for full-chip ESD-protection circuitry-design verification. Capability of the new tool is demonstrated using a practical design example in a 0.35-/spl mu/m BiCMOS technology.

The challenges for developing an on-chip electrostatic discharge (ESD) protection circuit layout extractor originate from unconventional layout patterns of ESD protection devices, parasitic ESD device extraction, and device count reduction. This paper reports a new technology independent layout extractor called the ESDExtractor, which is capable of extracting arbitrary ESD protection devices and answers the demands for full-chip ESD protection design verification. The general methodology to extract both intentional and parasitic ESD protection devices, the specific algorithms, and implementation methods to enhance ESDExtractor's efficiency are presented. Finally, the capability of the new computer-aided design tool is demonstrated using application examples.