The implementation of Network-on-Chip (NoC) architectures presents considerable advantages in performance relative to traditional bus-based systems. However, the sophisticated nature of NoC designs demands careful oversight of shared resources to mitigate potential performance issues. In this context, well-structured routing algorithms are essential, as they facilitate improved traffic management and minimize congestion. Furthermore, mechanisms for deadlock prevention and avoidance are integral to routing algorithms, ensuring continuous packet transmission and ultimately enhancing network performance. This paper introduces a novel reactive deadlock avoidance method for Triplet-Based Architecture Inter-Core NoC (TriBA-cNoC). that classifies routing based on Focus Routing Graph (FRG) size to address routing-level deadlocks caused by the combination of deterministic routing and TriBA-cNoC’s inherent network characteristics. Compared to proactive techniques, it improves downstream buffer utilization and reduces power consumption. Furthermore, two shortest-path routing algorithms are introduced: DM4T-M, which incorporates a round-robin selection mechanism to alleviate congestion on critical paths and minimize hot-node formation. TSR, a novel two-stage distributed routing algorithm, addresses the computational overhead associated with output port selection in previous algorithms. Simulation results obtained using gem5 show that the proposed approach, which integrates routing-level reactive deadlock avoidance with the proposed routing algorithms, yields improvements in latency, throughput, buffer utilization, and power consumption. TSR and DM4T-M achieve latency reductions of up to 34.89% and 28.2%, respectively. Throughput increases of up to 16.94% and 7.81% are observed for TSR and DM4T-M, respectively. Moreover, the proposed approaches enhance buffer utilization by up to 13.9% and 10.44%, while reducing power consumption by up to 9.64%.

Innovative processor architecture designs are shifting towards Many-Core Architectures (MCAs) to meet the future demands of high-performance computing as the limits of Moore’s Law have almost been reached. Many-core processors utilize shared memory hierarchies to achieve high-speed memory systems, improving memory access efficiency. However, as the number of cores multiplies, the scalability of this system is significantly constrained by the increased proportion of long-distance and Non-Uniform Memory Access (NUMA). Improving the scalability of MCAs is crucial for achieving large/super-scale general-purpose many-core processors. This work proposes a high-scalability memory Network-on-Chip (NoC) for Triplet-Based Many-Core Architecture (TriBA), named TriBA-mNoC. TriBA-mNoC maintains a consistent core-to-core spacing as the network scale increases, effectively preventing increased long-distance memory access latency. Moreover, it leverages an inherent advantage of shared-inside hierarchical-groupings, alleviating common NUMA issues in the NoC design. Evaluations of static network characteristics show that TriBA-mNoC outperforms most classical NoCs in network diameter, average distance, and cost. TriBA-mNoC can be integrated with TriBA in the same silicon die with a tile-like floorplan, forming a novel NoC called TriBA-NoC, which can combine the strengths of both networks to maximize the architecture performance. We evaluated the memory access performance and scalability of TriBA-NoC using the mathematical evaluation models and actual simulations with real traffic (PARSEC 3.0 and SPLASH-2) at different network scales. The mathematical evaluation results indicate that TriBA-NoC achieves an aggregate speedup of approximately 3x compared with 2D-Mesh for a similar number of cores. Furthermore, TriBA-NoC’s single-core speedup efficiency remains stable as the number of cores increases under the same cache hit ratio, whereas 2D-Mesh experiences a rapid decline, highlighting TriBA-NoC’s exceptional scalability. Finally, the actual traffic simulation results show that TriBA-NoC achieves an average memory access latency and time reduction of 25.90% to 40.50% and 5.61% to 31.69%, respectively, compared with 2D-Mesh.

The blood-brain barrier (BBB) plays a crucial role in protecting brain health by acting as a barrier between the brain and blood vessels. This barrier also presents challenges for delivering peptide drugs to brain targets. There is a pressing need for computational methods to accurately predict the permeability of peptides across the BBB. However, existing approaches face challenges due to limited real experimentally data and incomplete molecular information within peptide sequences. In this paper, we introduce MultiB3Pred, a multi-view deep learning method designed to address these challenges. Our method makes three key contributions. Firstly, we employ a effective amino acid replacement strategy for data augmentation. Secondly, We utilize sequence embeddings from a biologically pretrained model ProtT5 [1], further refined by a Transformer to capture dependencies on our specific dataset, leading to better sequence representations for the sequence predictor. Lastly, we derive SMILES from the sequences and train a novel SMILES learner. Precisely, the physicochemical properties of the molecules with the graph representation captured by the graph neural network from the molecular graphs are integrated through multilayer perceptron. The predicted probabilities from two sub-predictors are averaged to obtain the final result. Experiments demonstrate that MultiB3Pred achieves state-of-the-art accuracy and Matthews correlation coefficient of 94.4% and 89.9% respectively, showcasing its excellent performance in predicting blood-brain barrier penetration. At the same time, the stability of the model is confirmed by the good results of the 5-fold crossover experiment.

By transmitting task-related information only, semantic communications yield significant performance gains over conventional communications. However, the lack of mature semantic theory about semantic information quantification and performance evaluation makes it challenging to perform resource allocation for semantic communications, especially when multiple tasks coexist in the network. To cope with this challenge, we propose a quality-of-experience (QoE) based semantic-aware resource allocation method for multi-task networks in this paper. First, semantic entropy is defined to quantify the semantic information for different tasks, and the relationship between semantic entropy and Shannon entropy is analyzed. Then, we develop a novel QoE model to formulate the semantic-aware resource allocation in terms of semantic compression, channel assignment, and transmit power. The compatibility of the formulated problem with conventional communications is further demonstrated. To solve this problem, we decouple it into two subproblems and solved them by a developed deep Q-network (DQN) based method and a proposed low-complexity matching algorithm, respectively. Finally, simulation results validate the effectiveness and superiority of the proposed method, as well as its compatibility with conventional communications.