The semiconductor industry is adopting chiplets as an alternative to integrated circuit design. With adoption of off-the-shelf chiplets, supply chain attacks are likely to increase, making chiplet authentication essential. This work identifies post-stacking testing as the best phase for authentication and proposes a framework using existing industry standards. The framework includes a flexible authentication IP integrated into the chiplet design, compatible with various authentication methods; an IP insertion flow compatible with commercial DFT insertion tools; a secure module for the test environment; and the corresponding test procedure. Results show that chiplet authentication can be implemented without disrupting industry practices, with multiple authentication methods available based on the context.

Chiplet technology for 2.5-D/3-D integration is being rapidly adopted, including for System-on-Chips used in mission critical applications. We present a Total Ionizing Dose Effect study of a prototype Advanced Interface Bus (AIB) die-to-die interface in 28nm FD-SOI technology using pulsed x-rays and in-situ monitoring of the dose. Degradation of the maximum working frequency of the interface was observed due to the deposited dose. Using either the core voltage or the body bias voltage, we demonstrate that it is possible to partially recover this frequency loss. In space applications, this compensation, combined with in-situ dose monitoring, can be used to extend the life of 2.5-D/3-D circuits using high-speed die-to-die interfaces.

2.5D and 3D integrated circuits (IC) are the natural evolution of traditional 2D SoCs. 2.5D and 3D integration is the process of assembling pre-manufactured chiplets in an interposer or in a stack. This process can damage the chiplets or lead to faulty connections. Thus, the importance of post-bond test of chiplets. The IEEE Std 1838(TM)-2019 (IEEE 1838) design-for-testability (DFT) standard defines mandatory and optional structures for accessing DFT functions on the chiplet. Compliant chiplets form a DFT network that can be exploited by attackers to violate the confidentiality or integrity of the message transmitted over the serial path. In this work, we combine a message integrity verification system with a scan encryption mechanism to protect the scan chain of an IEEE 1838-compliant DFT implementation. The scan encryption prevents unauthorized actors from writing meaningful data into the scan chain. Message integrity verification makes messages from untrustworthy sources detectable. In conjunction, both security primitives protect the scan chain from malicious chiplets on the stack, scan-based attacks, and brute force attacks. The proposed solution causes less than 1% area overhead on designs composed of more than 5 million gates and less than 1% test time overhead for typical DFT implementations.

This paper introduces an Adaptive Power Management (APM) hardware module based on reinforcement learning techniques. The APM provides power consumption optimization during the suspend state of an Internet-of-Things (IoT) System-on-Chip (SoC) with 8 embedded power states. A Q-Learning algorithm with a counter-based exploration policy has been chosen and implemented. A complete analysis has been performed to properly define the parameters of the algorithm and characterize the proposed solution. A hardware implementation is also shown and introduces the APM design and simplification made for an Ultra Low Power hardware. This solution gives a long term average gain of 17% of power consumption during the system suspend time.

Todays' MPSoC applications are requiring a convergence between very high speed and ultra low power. Ultra Wide Voltage Range (UWVR) capability appears as a solution for high energy efficiency with the objective to improve the speed at very low voltage and decrease the power at high speed. Using Fully Depleted Silicon-On-Insulator (FDSOI) devices significantly improves the trade-off between leakage, variability and speed even at low-voltage. A full design framework is presented for UWVR operation using FDSOI Ultra Thin Body and Box technology considering power management, multi-VT enablement, standard cells design and SRAM bitcells. Technology performances are demonstrated on a ARM A9 critical path showing a speed increase from 40% to 200% without added energy cost. In opposite, when performance is not required, FDSOI enables to reduce leakage power up to 10X using Reverse Body Biasing.

Ultra-low voltage is now a well-known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. At 0.33V, it performs at 600 kHz with a dynamic energy consumption reduced by a factor 14x from nominal 1.1V. Based on this design, experiments, and preliminary silicon results, two additional libraries were developed in order to enhance future ultra-low voltage circuit performance.

Ultra-low voltage is now a well known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting-up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. It performs at 457 kHz, with a total energy consumption of 2.9fJ per cycle.