Per-survivor processing (PSP) is now seen as an attractive approach to performing maximum-likelihood sequence estimation (MLSE) over mobile radio channels that are rapidly time varying. An optimal PSP strategy incorporates statistical channel modeling and Kalman filtering. For severely time-dispersive channels, this approach becomes prohibitively complex. A novel filtering algorithm is presented to approximate Kalman PSP. MLSE with the new scheme offers a large reduction in computational complexity, and achieves performance close to the optimal Kalman approach and superior to existing PSP schemes in rapidly fading channels. The exact expressions presented for the pairwise error probability of MLSE with Kalman PSP may be used to predict the detector performance without resorting to lengthly simulations.

The well-known M-algorithm and the newer T-algorithm are two closely related reduced-complexity trellis-search algorithms that can be used for data sequence estimation in digital communication systems. VLSI implementations of these algorithms are attractive due to the parallelism and simplicity of their operation. While a small number of VLSI structures have been proposed previously, this paper describes new sorting-based architectures that can be used to realize these algorithms. Specifically, schemes based on odd-even transposition, insertion, and weavesorting techniques are presented. Structures are evaluated on the basis of area, time, and power measures. Actual VLSI implementations have been used to verify timing models.>

This proposal avoids the complex matched-filter bank required for optimal detection. Instead, two simple lowpass filters are employed, followed by a sampler and a Viterbi algorithm that accounts for ISI. For representative modulations it is shown that near-optimal performance can be achieved with just two samples per baud.>

It is shown, for a set of trial ISI channels, that two reduced-search breadth-first trellis decoders, namely the M-algorithm and the newer T-algorithm, can provide performance equivalent to reduced state sequence estimation (RSSE) but at a substantially reduced computational load. These algorithms allow the optional use of powerful codes and/or Tomlinson precoding.>

A breadth-first trellis decoding algorithm is introduced for application to sequence estimation in digital data transmission. The high degree of inherent parallelism makes a parallel-processing implementation attractive. The algorithm is shown to exhibit an error-rate versus average-computational-complexity behavior that is much superior to the Viterbi algorithm and also improves on the M-algorithm. The decoding algorithm maintains a variable number of paths as its computation adapts to the channel noise actually encountered. Buffering of received samples is required to support this. Bounds that are evaluated by trellis search are produced for the error event rate and average number of survivors. Performance is evaluated with conventional binary convolutional codes over both binary-synchronous-communication (BSC) and additive-white-Gaussian-noise (AWGN) channels. Performance is also found for multilevel AM and phase-shift-keying (PSK) codes and simple intersymbol interference responses over an AWGN channel. At lower signal-to-noise ratio Monte Carlo simulations are used to improve on the bounds and to investigate decoder dynamics.>

Several VLSI architectures for performing exponentiation in GF(2/sup m/) are presented. Two approaches to the architecture design are taken. In the first, all intermediate products of the exponentiation are computed in a sequential fashion to minimize the silicon area. In the second approach, all values of raised to the 2/sup ei/ power, O>

A nonsorting structure for implementing the (M, L) algorithm is presented. The processing is based on a survivor selection operation that incorporates parallelism and has an execution time proportional to the product of the logarithm of bM (the number of contender paths), and k (the number of bits used for path metrics). Aside from the path extender(s), the processor area is only a small fraction of the total chip area; most is simply for required storage of path histories and metrics. This means that the structure can support a large M on a single chip. In addition, the structure can be extended to larger M by stacking rows of a few different types of custom chips.>

Phase tracking capability is incorporated into two sequence estimation decoders for continuous phase modulations. One decoder employs the Viterbi algorithm; the other uses a reduced-survivor approach proposed earlier by one of the authors [11] for the more bandwidth efficient of these modulations. Computational complexity with the simplest of the joint data/phase algorithms is only marginally greater than that required for the equivalent decoding algorithm employing an externally derived carrier phase reference as supplied by a conventional carrier recovery circuit. Simulations with representative partial response modulations demonstrate the phase synchronization and tracking capabilities of the decoders. High SNR losses relative to an optimal receiver having perfect phase knowledge are found to be small (∼ 1 dB).

Digital angle modulations having input symbol memory can be demodulated using maximum likelihood sequence estimation (MLSE or Viterbi decoding). The demodulation of the more bandwidth efficient of these can require a large number of computations. In this paper, lower complexity decoding approaches are presented. These decoders use a predetermined processing order and a reduced number of survivor signals,S, at every-timeNT. Processing is performed on the signal sequences using metrics (likelihoods) obtained by a matched filter bank similar to that needed for MLSE. The decoders can achieve asymptotic optimality of error rate while being computationally faster and simpler than MLSE for many modulations. In addition, error rate performance can be traded for complexity reduction. Expected performance has been verified for representative modulations.