Demo Data from EDBT 2026 / reviewers in the wild / expert
Werner Buchholz
dblp:95/1148
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 1988
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Processor architecture and microarchitecture · 85% Memory systems · 15% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture
vector processor |
0.0 | 2 | 1988 | The IBM System/370 Vector Architecture: Design Considerations · IEEE Trans. Computers 1988 Concepts of the System/370 Vector Architecture · ISCA 1987 |
Processor architecture and microarchitecture
instruction set architecture |
0.0 | 2 | 1987 | Concepts of the System/370 Vector Architecture · ISCA 1987 Processing Data in Bits and Pieces · IRE Trans. Electron. Comput. 1959 |
Processor architecture and microarchitecture
vector processing |
0.0 | 1 | 1988 | The IBM System/370 Vector Architecture: Design Considerations · IEEE Trans. Computers 1988 |
Memory systems
cache |
0.0 | 1 | 1987 | Concepts of the System/370 Vector Architecture · ISCA 1987 |
Memory systems › memory access patterns
strided access |
0.0 | 1 | 1987 | Concepts of the System/370 Vector Architecture · ISCA 1987 |
Processor architecture and microarchitecture
computer arithmetic |
0.0 | 1 | 1959 | Processing Data in Bits and Pieces · IRE Trans. Electron. Comput. 1959 |
Methods — techniques the papers use, named apart from their topics
architectural analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1988 | The IBM System/370 Vector Architecture: Design ConsiderationsabstractThe considerations that shaped the architecture of the IBM System/370 Vector Facility are reviewed. The architectural requirements, decisions, and innovations are summarized, and the rationale for the choices that were made is given. Issues related to vector function, performance, compatibility, migration, and integration with the rest of the System/370 architecture are covered.> Andris Padegs, Brian B. Moore, Ronald M. Smith, Werner Buchholz |
IEEE Trans. Computers | 4 |
| 1987 | Concepts of the System/370 Vector ArchitectureabstractThis paper discusses the performance, complexity and system-integration considerations that shaped the System/370 Vector Architecture [1, 9]. The architecture is intended for compatible systems providing a range of price and performance. The paper reviews the reasons for choosing a register-oriented architecture with compound instructions over storage-to-storage operations and vector-instruction chaining. Then it discusses the role of cache in stride-N storage accessing, and describes some new facilities introduced for control-program purposes. Brian B. Moore, Andris Padegs, Ronald M. Smith, Werner Buchholz |
ISCA | 4 |
| 1959 | Processing Data in Bits and PiecesabstractA data-handling unit is described which permits binary or decimal arithmetic to be performed on data fields of any length from one to sixty-four bits. Within the field, character structure can be further specified: these processing entities, called bytes, may be from one to eight bits long. Fields may be stored with or without algebraic sign. On all operations, the relative offset or shift between the operand from memory and that from the accumulator can be specified. Besides the arithmetic operations, three new logical instructions allow any of the sixteen logical connectives of two variables to operate upon each pair of bits in the memory and accumulator operands. The variable field length, variable byte-size features, extend the use of connective operations to a surprisingly wide variety of logical, house-keeping, and editing tasks. These arithmetic and connective instructions are general and powerful programming tools which greatly simplify complex manipulations. Programming of typical tasks, with both the new instructions and with the instruction set of a conventionally-organized computer, has shown that the new set requires substantially fewer instructions to be written, stored, and executed. Furthermore, the new instruction set has considerably fewer distinct operations than the more conventional set. This is possible because the general-purpose instructions of the new set replace many ad hoc instructions which deal with pieces of instructions or data words, or which perform shifting, packing, or editing functions. The initial application of the variable field length data-processing unit is in the IBM Stretch computer. Frederick P. Brooks Jr., Gerrit A. Blaauw, Werner Buchholz |
IRE Trans. Electron. Comput. | 3 |