This paper describes a receiver front-end that is designed to realize multi-gigabit data communication via large-core plastic optical fiber (POF) in deep submicron CMOS technology. A 3D system-level integration scheme and transistor level circuits have been proposed for such a low-cost, high-speed POF receiver. With 44 mW (excluding output driver) DC power dissipated from a 1.2 V supply and an estimated 13 pF photo capacitance (CPD) from a discrete, large-area (400 um) photo detector (PD), a data rate of 3 Gbps, with a sensitivity of -11 dBm (BER = 10-12), has been simulated in STMicroelectronics (STM) 65 nm low-power CMOS technology.

As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic effects limiting matching accuracy, electromigration effects limiting conductor lifetime, leakage and mobility effects limiting device performance, and chip power dissipation limits driving individual circuits to be more energy-efficient. The lack of analog design and simulation tools available to address these problems has become the focus of a significant effort with the electronic design automation industry. Postlayout simulation tools are not useful during the design phase, while technology computer-aided design physical simulation tools are slow and not in common use by analog circuit designers. In the nanoscale era of analog CMOS design, an understanding of the physical factors affecting circuit reliability and performance, as well as methods of mitigating or overcoming them, is becoming increasingly important. The first part of the paper presents factors affecting device matching, including those relating to single devices as well as local and long-distance matching effects. Several reliability effects are discussed, including physical design limitations projected for future downscaling. In some cases, it may be helpful to exceed foundry-specified drain-source voltage limits by a few hundred millivolts. Models are presented for achieving this, which include the dependence on the shape of the output waveform. The conditionVsb> 0 is required for cascode circuit configurations. The role of other terminal voltages is discussed, asVsb> 0 increases both hot and cold carrier damage effects in highly scaled devices. The second part of the paper focuses on trends in device characteristics and how they influence the design of nanoscale analog CMOS circuits. A number of circuit design techniques employed to address the major nonidealities of nanoscale CMOS technologies are discussed. Examples include techniques for establishing on-chip accurate and temperature-insensitive bias currents, digital calibration of analog circuits, and the design of regulator and high-voltage circuits. Achieving high energy efficiency in ICs capable of accommodating 109devices is becoming critically important. This paper also presents a survey of the evolution of figure of merit for analog-to-digital converters.

This paper presents design methods for delta-sigma (ΔΣ) analog to digital (A/D) converters having signal-transfer functions (STFs) with improved out-of-band signal attenuation. The trade-off between the improved attenuation of the STF and achieving a noise-transfer function (NTF) that optimizes the SNR of the A/D converter is made explicit.

Offset, gain, and sample-time mismatches among different channels of a time-interleaved analog-to-digital converter (ADC) are causes of significant degradation of performance. Compensation techniques for offset mismatch, gain mismatch, and sample-time error in time-interleaved ADCs are proposed. The compensation methods use random digital data and do not use a calibration signal. The offset and gain mismatches are corrected in digital domain, while the timing error correction is performed by adjusting the delay of the clock path of each channel, using a digitally-controlled delay element. The simulation results verify that the proposed compensation techniques estimate and correct offset mismatch, gain mismatch and timing error with a high degree of accuracy. These low complexity techniques are especially suitable for time-interleaved ADCs used in digital data communication systems

A method for generating on-chip time-constants with accuracy limited by that of on-chip capacitors is presented. The technique uses an adjustable constant-g/sub m/ bias-circuit along with a fully-integrated charge-pump CMOS PLL with a free-running frequency of 250 MHz. The VCO is composed of an adjustable constant-g/sub m/ bias circuit, which controls a g/sub m/-controlled oscillator. The PLL is used to lock the VCO to a crystal reference, which causes the bias circuit to generate a certain well-known transconductance. The bias circuit then biases circuits with well-defined time-constants, since they are inversely proportional to transistor transconductances. The design has been fabricated in a 0.35 /spl mu/m CMOS process, using an area of 1600/spl times/1600 /spl mu/m/sup 2/.

A decision-directed carrier-recovery technique for coherent demodulation of quadrature amplitude modulated (QAM) signals is proposed. This system adaptively tracks both the carrier frequency and phase of the received QAM signal's modulated carrier. The acquisition time of the proposed system is shown to be faster than that of conventional carrier-recovery schemes, especially when the initial carrier-frequency offset is relatively large, i.e. beyond a small fraction of the symbol rate. Also, the proposed method has a wider acquisition range compared to conventional techniques.

A new architecture is proposed for a single-chip digital radio receiver. This architecture has several advantages over the direct-conversion architecture that has been gaining interest for use in single-chip designs. A non-zero quadrature IF reduces the image problem and eliminates concerns about self-EMI and 1/f noise. A complex bandpass filter embedded in a delta-sigma loop allows the A/D conversion to be performed directly on the pair of quadrature outputs from the mixer.>

Viterbi detectors have traditionally been realized in digital hardware and/or software. However, analog implementations can lead to smaller, faster and lower power-consumption circuits. In this paper, a new architecture for realizing a class-IV partial-response Viterbi detector is proposed and implemented using simple analog building blocks. This architecture is more robust against offsets and gain errors than other analog detectors and should operate faster when implemented in the same technology. In addition, it is shown that the Viterbi detector is an adaptive-threshold device with a complexity much less than that of a typical 6-bit A/D convertor required in digital realizations. Performance of the detector is evaluated by simulations and experimental results.>

An infinite impulse response (IIR) adaptive filter that is efficient and can be used to analyze short data segment with high resolution and very small biases is presented. The approach taken is to run the short data segment continuously forwards and backwards in time through the adaptive filter. The proposed adaptive filter is a filter bank composed of a number of parallel digital resonators with common feedback around all of them. Because of this particular architecture, the filter is easy to reset the internal state variables of the adaptive filter each time the direction of the input data segment is changed. This allows the same data segment to be run through the adaptive filter many times, with the adaptive filter converging closer to its optimum state each time. No windowing is required, which results in higher accuracies when determining the sinusoidal components of the input data. The resonator frequencies are adapted to match the frequencies of the input data segment. When the adaptive filter has converged, the isolated input sinusoids are available at the outputs of the resonators.>

Comparisons of the performance of different types of correlator receivers and the limiter-discriminator for FSK (frequency shift keying) demodulation are presented, based on a modification of the analysis used by N. Ekanayake (1984), which allows the IF (intermediate frequency) bandlimiting to be taken into account. It is shown that for optimal values of IF bandwidth and deviation ratio, all receivers perform about the same, hence, the choice of receiver type can be made based on implementational considerations. To this end, the signal-to-interference ratio is introduced as a possible criterion for selecting the receiver type. Further, some of the correlator types considered possess the capability of being tuned, allowing them to perform better for larger values of the deviation ratio and IF bandwidth. It is shown that the conditions for optimal Pe performance of FSK are modified when sampling offset is considered.>

Two power-normalized update algorithms for adaptive filters that do not require divisions are described. The algorithms are based on very simple iterative procedures that approximate divisions. Since neither the quotients nor the dividends change quickly, the division procedures need only be updated once each time the coefficients of the adaptive filter are updated. The new update algorithms result in adaptive filters only slightly more complex than steepest descent adaptive filters. The algorithms are especially applicable to real-time adaptive filters realized using single chip digital signal processors or custom ASICs (application-specific integrated circuits), where hard-wired dividers are usually not available and fast convergence is still desired.>