Remote attestation is a powerful mechanism that allows a verifier to know if the hardware of an IoT (Internet-of-Thing) device (acting as a prover) has been counterfeited or tampered with and if its firmware has been altered. Remote attestation is based on collecting and reporting measurements in a trusted way, and should be lightweight for resource-constrained IoT devices. This work proposes to include a low-cost Root of Trust for Measuring and Reporting (RoTMR) in the prover, based on the combination of a Physically Unclonable Function (PUF) and an Attestation Read-Only Memory (A-ROM), and to use hash-based digital signatures in the attestation protocol. The proposed RoTMR is addressed to IoT devices based on a microcontroller that executes some application code (the measurable object) located in an external non-volatile memory accessible by an attacker. The secret keys required by the digital signatures are not stored but reconstructed using the PUF. The A-ROM contains the attestation instructions and ensures that its contents cannot be altered and that its instructions are executed sequentially without modification. The use of hash-based digital signatures makes the solution quantum-resistant and very robust because its security relies solely on the unidirectionality of a hash function. The proposed attestation protocol takes advantage of the fact that One-Time Signature (OTS) generation and Many-Time Signature (MTS) verification are very well suited for low-end devices, and the MTS scheme is suitable for the verifier application context. The proposal was validated experimentally with the ESP32 microcontroller, which is widely employed in IoT devices, by using its SRAM as PUF and implementing WOTS+, which is a type of Winternitz One-Time Signature scheme (WOTS), the One-Time Signature of Smart Digital Signatures scheme (SDS-OTS), and the MTS schemes constructed with them. The OTS schemes require smaller codes and thus smaller A-ROM than MTS and ECDSA (Elliptic Curve Digital Signature Algorithm). The code of one of the WOTS+ takes about 4 times less space than ECDSA. In terms of execution times, the OTS schemes are very fast. One of the WOTS+ performs all the signature operations in a few tens of milliseconds. The OTS schemes (especially the SDS-OTS) are also very efficient in terms of communication bandwidth because they use small signatures compared to other post-quantum solutions.

Physically unclonable functions (PUFs) and true random number generators (TRNGs) are cryptographic primitives very well suited for secure IoT devices. This article proposes a circuit, named multibit-RO-PUF-TRNG, which offers the advantages of unifying PUF and TRNG in the same design. It is based on counting the oscillations of pairs of ring oscillators (ROs), one of them acting as a reference. Once the counter of the reference oscillator reaches a fixed value, the count value of the other RO is employed to provide the TRNG and the multibit PUF response. A mathematical model is presented that supports not only the circuit foundations but also a novel and simple calibration procedure that allows optimizing the selection of the design parameters. Experimental results are illustrated with large data sets from two families of FPGAs with different process nodes (90 and 28 nm). These results confirm that the proposed calibration provides TRNG and PUF responses with high quality. The raw TRNG bits do not need post-processing and the PUF bits (even 6 bits per RO) show very small aliasing. In the application context of obfuscating and reconstructing secrets generated by the TRNG, the multibit PUF response, together with the proposal of using error-correcting codes and RO selection adapted to each bit, provide savings of at least 79.38% of the ROs compared to using a unibit PUF without RO selection. The proposal has been implemented as an APB peripheral of a VexRiscv RV32I core to illustrate its use in a secure FPGA-based IoT device.

This paper describes a demonstrator of a post-quantum-secure facial authentication system distributed between a mobile device acting as a client and a remote computer acting as an authentication server. Homomorphic encryption based on Classic McEliece, one of the fourth-round candidates of the NIST post-quantum standardization process, is carried out by the client for protecting the biometric data extracted from the users' faces at enrollment and verification. The remote computer only stores and compares the received protected data, thus preserving user privacy. An Android App and a Graphical User Interface (GUI) were implemented at the client and the server, respectively, to show the system performance in terms of computation and security.

A large number of rules increases the complexity of fuzzy classifiers and reduces the linguistic interpretability of the classification. A tabular rule simplification method that extends the Quine-McCluskey algorithm of Boolean design to fuzzy logic is analyzed in detail in this paper. The method obtains a few compound rules from many initial atomic rules. The influence of membership functions as well as t-norms and s-norms operands, which can be even null if many atomic rules are used, becomes apparent in the classification regions (decision boundaries) induced by the compound rules. Since the compound rules can be ordered according to the covering indexes that measure the number of atomic rules covered, more or less generic classification rules and rules with particular indexes can be further identified, which could ease subsequent classification or decision-making.

This paper presents a methodology to approximate explicit Model Predictive Control (MPC) laws by hierarchical fuzzy systems, particularly piecewise-affine hierarchical (PWAH) systems. These hierarchical controllers provide high operation speed with low cost in computational and memory resources because they are formed only by single-input and single-output (SISO) fuzzy modules connected in cascade. The methodology employs the CAD tools of Xfuzzy environment to describe, adjust, verify, and implement the controllers in a Field Programmable Gate Array (FPGA). The methodology is illustrated with the design and FPGA implementation of a hierarchical controller for a car adaptive cruise control (ACC) system. The resulting controller is better in terms of speed and FPGA resource consumption than other solutions reported in the literature.

This paper provides a mathematical model that describes how deterministic and Gaussian jitter of an oscillating signal accumulated during a time interval are related to the bits of the binary-coded count value of the oscillations. The model is employed to propose a robust TRNG that has a simple interface (an initialization signal as input and the random bits as output) and that features auto-calibration to certify high entropy of the raw bits provided as well as to work at the highest throughput allowed by the available local Gaussian noise. The mathematical analysis is confirmed with experimental results of ring oscillator (RO) TRNGs described in VHDL and implemented in the programmable logic of Zynq family Xilinx FPGAs, using either another RO or the clock of the FPGA board to control the time interval of oscillations.

This paper proposes an access control system based on the simultaneous authentication of what the user has and who the user is. At enrollment phase, the wearable access device (a smart card, key fob, etc.) stores a template that results from the fusion of the intrinsic device identifier and the user biometric identifier. At verification phase, both the device and user identifiers are extracted and matched with the stored template. The device identifier is generated from the start-up values of the SRAM in the device hardware, which are exploited as a Physically Unclonable Function (PUF). Hence, if the device hardware is cloned, the authentic identifier is not generated. The user identifier is obtained from level-1 fingerprint features (directional image and singular points), which are extracted from the fingerprint images captured by the sensor in the access device. Hence, only genuine users with genuine devices are authorized to access and no sensitive information is stored or travels outside the access device. The proposal has been validated by using 560 fingerprints acquired in live by an optical sensor and 560 SRAM-based identifiers.

Nowadays, several smart lock systems use Bluetooth Low Energy (BLE) to stablish a wireless communication between the physical key (key fob, card, smartphone, etc.) and the lock. Security is based on creating and storing secret digital keys to establish a cryptographically secure communication. The problem is that several attacks can break such security, particularly the copy of the physical key. In order to increase the difficulty of the attacks, the physical keys described in this paper do not store the secret cryptographic keys but reconstruct them when they are needed and remove them when they are not used. Only the trusted physical keys are able to reconstruct the secrets with the public data stored in them. This is possible by using the start-up values of the SRAM in the BLE chip of the physical key, which acts as a physical unclonable function (PUF), so that if the physical key is copied, the lock cannot be opened. The idea has been proven with the development of a smart lock system with key fobs based on the CC2541 BLE system on chip from Texas Instruments. Experimental results are included to illustrate the performance.

This paper presents a method to simultaneously improve the quality of the identifiers, secret keys, and random numbers that can be generated from the start-up values of standard static random access memories (SRAMs). The method is based on classifying memory cells after evaluating their start-up values at multiple measurements in a registration phase. The registration can be done without unplugging the device from its application context, and with no need for a complex laboratory setup. The method has been validated experimentally with standard low-power SRAM modules in two different application specific integrated circuits (ASICs) fabricated with the 90-nm TSMC technology. The results show that with a simple registration the length of the identifiers can be reduced by 45%, the worst case bit error probability (which defines the complexity of the error correcting code needed to recover a secret key) can be reduced by 64%, and the worst case minimum entropy value is improved, thus reducing the number of bits that have to be processed to obtain full entropy by 81%. The method can be applied to standard digital designs by controlling the external power supply to the SRAM using software or by incorporating simple circuitry in the design. In the latter case, a module for implementing the method in an ASIC designed in the 90-nm TSMC technology occupies an active area of 42, 025 μm2.

Lightweight security is currently a challenge in the field of cryptography. Most of applications designed for embedded scenarios often focus on authentication or on providing some form of anonymity and/or privacy. A well-known cryptographic element employed to provide such security is the HMAC construction. However, reported solutions are not suitable for constrained-resource scenarios due to their heavy approaches optimized for high-speed operations. In order to cover this lack, a lightweight implementation of HMAC based on the Photon family of hash functions is given in this work. Security of the construction against differential power attacks (DPA) is analyzed using a SASEBO-II development board. Implementation and performance results for Xilinx Virtex-5 FPGAs of the HMAC structure is provided.

The complexity reached by current applications of industrial control systems has motivated the development of new computational paradigms, as well as the employment of hybrid implementation techniques that combine hardware and software components to fulfill system requirements. On the other hand, continuous improvements in field-programmable devices today make possible the implementation of complex control systems on reconfigurable hardware, although they are limited by the lack of specific design tools and methodologies to facilitate the development of new products. This paper describes a model-based design approach for the synthesis of embedded fuzzy controllers on field-programmable gate arrays (FPGAs). Its main contributions are the proposal of a novel implementation technique, which allows accelerating the exploration of the design space of fuzzy inference modules, and the use of a design flow that eases their integration into complex control systems and the joint development of hardware and software components. This design flow is supported by specific tools for fuzzy systems development and standard FPGA synthesis and implementation tools, which use the modeling and simulation facilities provided by the Matlab environment. The development of a complex control system for parking an autonomous vehicle demonstrates the capabilities of the proposed procedure to dramatically speed up the stages of description, synthesis, and functional verification of embedded fuzzy controllers for industrial applications.

This paper presents a new modeling language for fuzzy systems called XFSML. It is an XML-based language and it is proposed as a starting point for the definition of a standard modeling language in the fuzzy community. The main features of the language are its high expressiveness and its independence from specific platforms, tools or programming languages.

Many studies have been directed to probe ring oscillator PUF's feasibility in the security field, but most of them suffer from the lack of global approach as they analyze the system isolated, giving an uncompleted theory about their behavior. This paper presents how adjacent hardware elements may affect PUF response, modifying their statistical characteristics and even masking the randomness of manufacturing process. This is a factor that should be taken into account when modeling the behavior of the ring oscillators in the PUF. Experimental results from Xilinx Spartan 3 FPGAs illustrate these issues.

This paper describes a design methodology to implement on FPGAs piecewise-affine (PWA) functions based on representation methods from the lattice theory. An off-line automatic processing starts at the algorithmic formulation of the problem, obtains the parameters required by a parameterized digital architecture, and ends with the bitstream to program an FPGA. The methodology has been proven to implement PWA functions on Xilinx FPGAs. The results are compared with other approaches for FPGA implementations of PWA functions.

This paper describes a methodology to extract fuzzy models that describe linguistically the low-level features of an image (such as color, texture, etc.). The methodology combines grid-based algorithms with clustering and tabular simplification methods to compress image information into a small number of fuzzy rules with high linguistic meaning. All the steps of the methodology are carried out with the help offered by the tools of Xfuzzy 3 environment, so we can define, simplify, tune and verify the fuzzy models automatically. Several examples are included to illustrate the advantages of the methodology.

The tuning of hierarchical fuzzy systems are not supported by the majority of CAD tools available at the market currently. The xfsl tool integrated into Xfuzzy 3 allows the tuning of complex fuzzy systems, for instance, hierarchical systems with modules in cascade. The authors propose the use of this tool for tuning a complex fuzzy system for video de-interlacing in this paper. The parameters obtained after tuning are proven by de-interlacing a wide battery of sequences. The use of tuning techniques improves the quality of de-interlacing and provides an algorithm simplification that facilitates its hardware implementation.

This paper presents a design environment for the synthesis of embedded fuzzy controllers on FPGAs. It provides a novel implementation technique that allows accelerating the exploration of the design space of fuzzy control modules, as well as a codesign flow that eases their integration into complex control systems and the joint development of hardware and software components. The set of CAD tools supporting this environment includes specific fuzzy logic design tools provided by Xfuzzy, FPGA synthesis and implementation tools from Xilinx, and modeling and simulation facilities from Matlab. As demonstrated by the analyzed design examples, the described development strategy takes advantage of flexibility and ease of configuration offered by the different tools to dramatically speed up the stages of description, synthesis, and functional verification of embedded fuzzy control systems.

This paper describes how the different CAD tools of the environment Xfuzzy 3, developed in Microelectronics Institute of Seville and University of Seville, allow to translate expressive linguistic models into mathematical ones, in particular, into a combination of piecewise polynomial systems that can be implemented efficiently in hardware. The new synthesis tool of Xfuzzy 3 automates communication with Xilinx System Generator in Matlab, thus facilitating implementation of the linguistic model into an FPGA from Xilinx. This is illustrated with the design of a navigation controller for an autonomous robot.

This paper describes how the combination of neuro-fuzzy techniques with geometric analysis offers a good trade-off between purely heuristics and purely physical approaches when solving the problem of car-like robot navigation. The controller described, which follows a reactive technique, generates trajectories of near-minimal lengths when no obstacles are detected and, in presence of obstacles, generates minimum deviations from them. All these reference paths meet the kinematic constraints of car-like robots and take into account dynamic issues. Besides its efficiency, the proposed controller is very simple and linguistically interpretable. The whole controller has been designed and verified by using the CAD tools of the Xfuzzy environment.

Since 1992, Xfuzzy environment has been improving to ease the design of fuzzy systems. The current version, Xfuzzy 3, which is entirely programmed in Java, includes a wide set of new featured tools that allow automating the whole design process of a fuzzy logic based system: from its description (in the XFL3 language) to its synthesis in C, C++ or Java (to be included in software projects) or in VHDL (for hardware projects). The new features of the current version have been exploited in different application areas such as autonomous robot navigation and image processing.

Simplification is an important step in the design of a fuzzy system since the membership functions that represent the fuzzy sets as well as the 'if-then' rules that relate them usually contain redundant information. This paper presents a CAD tool which provides the user with a wide set of algorithms to automate simplification process. It allows reducing the number of membership functions and rules described initially as well as increasing its expressiveness and linguistic interpretability. Since the tool is included within the design environment Xfuzzy 3, the simplified system can be also verified, tuned and synthesized automatically. Several examples are included to illustrate the efficiency of the simplification facilities provided.

This paper presents a study of the different kinds of membership function (MF) definitions, regarding free MFs and families of MFs, and describes the capabilities of XFL3 (the formal specification language defined by Xfuzzy 3) to manage them. This includes not only the possibility of using them in a system design, but also the capability for extending the available functions with new user-defined membership functions and families. An application example has been included in order to discuss on the suitable parametric definition of the functions.

This paper describes the design and implementation of a fuzzy control system for a car-like autonomous vehicle. The problem addressed is the diagonal parking in a constrained space, a typical problem in motion control of nonholonomic robots. The architecture proposed for the fuzzy controller is a hierarchical scheme which combines seven modules working in series and in parallel. The rules of each module employ the adequate fuzzy operators for its task (making a decision or generating a smoothly varying control output), and they have been obtained from heuristic knowledge and numerical data (with geometric information) depending on the module requirements (some of them are constrained to provide paths of near-minimal lengths). The computer-aided design tools of the environment Xfuzzy 3.0 (developed by some of the authors) have been employed to automate the different design stages: 1) translation of heuristic knowledge into fuzzy rules; 2) extraction of fuzzy rules from numerical data and their tuning to give paths of near-minimal lengths; 3) offline verification of the control system behavior; and 4) its synthesis to be implemented in a true robot and be verified on line. Real experiments with the autonomous vehicle ROMEO 4R (designed and built at the Escuela Superior de Ingenieros, University of Seville, Seville, Spain) demonstrate the efficiency of the described controller and of the methodology followed in its design.

Tuning a fuzzy system to meet a given set of input/output patterns is usually a difficult task that involves many parameters. This paper presents an study of different approaches that can be applied to perform this tuning process automatically, and describes a CAD tool, named xfsl, which allows applying a wide set of these approaches: (a) a large number of supervised learning algorithms; (b) different processes to simplify the learned system; (c) tuning only specific parameters of the system; (d) the ability to tune hierarchical fuzzy systems, systems with continuous output (like fuzzy controller) as well as with categorical output (like fuzzy classifiers), and even systems that employ user-defined fuzzy functions; and, finally, (e) the ability to employ this tuning within the design flow of a fuzzy system, because xfsl is integrated into the fuzzy system development environment Xfuzzy 3.0.

The crecient use of fuzzy systems in complex applications has motivated us to develop a new version of Xfuzzy, the design environment for fuzzy system created at the IMSE (Instituto de Microelectronica de Sevilla). This new version, Xfuzzy 3.0, offers the advantages of being enterely programmed in Java, and allows designing hierarchical rule bases that can interchange fuzzy or non fuzzy values as well as employ user-defined fuzzy connectives, linguistic hedges, membership functions, and defuzzification methods. Xfuzzy 3.0 integrates tools that facilitate the description, tuning, verification, and synthesis of complex fuzzy systems. This is illustrated in this paper with the design of a fuzzy controller to solve a parking problem.

This paper discusses architectural and circuit-level aspects related to hardware realizations of fuzzy controllers. A brief overview on fuzzy inference methods is given focusing on chip implementation. The singleton or zero-order Sugeno's method is chosen since it offers a good tradeoff between hardware simplicity and control efficiency. The CMOS microcontroller described herein processes information in the current-domain, but input-output signals are represented as voltage to ease communications with conventional control circuitry. Programming functionalities are added by combining analog and digital techniques, giving rise to a versatile microcontroller, capable of solving different control problems. After identifying the basic component blocks, the circuits used for their implementation are discussed and compared with other alternatives. This study is illustrated with the experimental results of prototypes integrated in different CMOS technologies.