EDBT 2026 Demo / reviewers in the wild / expert
Tsuneo Inufushi
dblp:95/1324
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2000
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 96% Integrated circuit design · 4% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.0 | 2 | 1982 | A placement algorithm for polycell LSI and ITS evaluation · DAC 1982 SHARPS: A hierarchical layout system for VLSI · DAC 1981 |
Electronic design automation › physical design
placement |
0.0 | 1 | 1982 | A placement algorithm for polycell LSI and ITS evaluation · DAC 1982 |
Electronic design automation › physical design
routing |
0.0 | 1 | 1982 | A placement algorithm for polycell LSI and ITS evaluation · DAC 1982 |
Electronic design automation › physical design › layout analysis
hierarchical layout analysis |
0.0 | 1 | 1981 | SHARPS: A hierarchical layout system for VLSI · DAC 1981 |
Electronic design automation › physical design
layout system |
0.0 | 1 | 1981 | SHARPS: A hierarchical layout system for VLSI · DAC 1981 |
Integrated circuit design
VLSI design |
0.0 | 1 | 1981 | SHARPS: A hierarchical layout system for VLSI · DAC 1981 |
Methods — techniques the papers use, named apart from their topics
iterative improvement · 0.0hierarchical layout · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2000 | A high-speed IDDQ sensor implementationabstractThis paper presents an effective IDDQ sensor design implemented using a 0.35 /spl mu/m process. A straightforward feedback scheme minimizes the effect of process variations. Independent structures permit one to monitor the basic characteristics of the IDDQ sensor, i.e., resolution and speed, and to carry out a 20k-gate floppy-disk controller IDDQ test separately. Simulation and test results show accuracy better than /spl plusmn/10 /spl mu/A at 50 MHz in a 1 mA IDDQ measurement range. Yann Antonioli, Tsuneo Inufushi, Shigeki Nishikawa, Kozo Kinoshita |
Asian Test Symposium | 2 |
| 1982 | A placement algorithm for polycell LSI and ITS evaluation
Takashi Kambe, Toru Chiba, Seiji Kimura, Tsuneo Inufushi, Noboru Okuda, Ikuo Nishioka |
DAC | 4 |
| 1981 | SHARPS: A hierarchical layout system for VLSI
Toru Chiba, Noboru Okuda, Takashi Kambe, Ikuo Nishioka, Tsuneo Inufushi, Sieji Kimura |
DAC | 5 |