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Alfred L. Burress

dblp:95/1612 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1999
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 50% Reconfigurable computing and FPGAs · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › FPGA architecture
LUT-based FPGA		 0.011999
Self-Checking Logic Design for LUT-Based FPGAs · FPGA 1999
Hardware reliability and fault tolerance
self-checking circuits		 0.011999
Self-Checking Logic Design for LUT-Based FPGAs · FPGA 1999
YearPublicationVenuePosition
1999 Self-Checking Logic Design for LUT-Based FPGAs
Parag K. Lala, Alfred L. Burress
 FPGA2
1997 On-Line Testable Logic Desgin for FPGA Implementation
abstract
In recent years, a number of logic design techniques for look-up table (LUT) based FPGAs have been proposed. However, none of these address issues such as fault detection or testability. This paper presents an algorithm which maps optimized Boolean expressions into look-up table based FPGAs. This mapping automatically incorporates testability features into designs, allowing on-line detection of faults within a FPGA. This is accomplished by utilizing a unique set of cells to implement a design. These cells operate on the premise of a two-rail checker, thus producing both the normal and complemented output when a cell is operating correctly, and two outputs of the same value in the presence of a fault. Faults generated in an intermediate cell is propagated to the final outputs, thus allowing on-line testability of a FPGA-based logic system.
Alfred L. Burress, Parag K. Lala
 ITC1