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Michael Deisher

dblp:95/2309 · DBLP profile ↗
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7ranked-venue papers
1as first author
1since 2021 · last 2023
0009-0007-5391-1261ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Graphics, computer vision, multimedia, augmented reality and games · 6 · 1 first-author · 1 since 2021Artificial intelligence and machine learning · 1Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 61% GPUs and heterogeneous computing · 30% Processor architecture and microarchitecture · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation
benchmarking
0.112010
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU · ISCA 2010
GPUs and heterogeneous computing
GPU computing
0.112010
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU · ISCA 2010
Performance modeling and evaluation
throughput computing
0.112010
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU · ISCA 2010
Processor architecture and microarchitecture
chip multiprocessor
0.012010
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU · ISCA 2010

Methods — techniques the papers use, named apart from their topics

performance analysis · 0.1optimization techniques · 0.1
YearPublicationVenuePosition
2023 An End-to-End Neural Network for Image-to-Audio Transformation
abstract
This paper describes an end-to-end (E2E) neural architecture for the audio rendering of small portions of display content on low resource personal computing devices. It is intended to address the problem of accessibility for vision-impaired or vision-distracted users at the hardware level. Neural image-to-text (ITT) and text-to-speech (TTS) approaches are reviewed and a new technique is introduced to efficiently integrate them in a way that is both efficient and back-propagate-able, leading to a non-autoregressive E2E image-to-speech (ITS) neural network that is efficient and trainable. Experimental results are presented showing that, compared with the non-E2E approach, the proposed E2E system is 29% faster and uses 19% fewer parameters with a 2% reduction in phone accuracy. A future direction to address accuracy is presented.
Liu Chen, Michael Deisher, Munir Georges
ICASSP2
2020 Structural Sparsification for Far-Field Speaker Recognition with Intel® Gna
abstract
Recently, deep neural networks (DNN) have been widely used in speaker recognition area. In order to achieve fast response time and high accuracy, the requirements for hardware resources increase rapidly. However, as the speaker recognition application is often implemented on mobile devices, it is necessary to maintain a low computational cost while keeping high accuracy in far-field condition. In this paper, we apply structural sparsification on time-delay neural networks (TDNN) to remove redundant structures and accelerate the execution. On our targeted hardware, our model can remove 60% of parameters and only slightly increasing equal error rate (EER) by 0.18% while our structural sparse model can achieve more than 1.5× speedup.
Jingchi Zhang, Jonathan Huang, Michael Deisher, Hai Li 0001, Yiran Chen 0001
ICASSP3
2019 Learning Efficient Sparse Structures in Speech Recognition
abstract
Recurrent neural networks (RNNs), especially long short-term memories (LSTMs) have been widely used in speech recognition and natural language processing. As the sizes of RNN models grow for better performance, the computation cost and therefore the required hardware resource increase rapidly. We propose an efficient structural sparsity (ESS) learning method for acoustic modeling in speech recognition. ESS aims to generate a model that offers higher execution efficiency while maintaining the accuracy. A three-step training pipeline is developed in our work. First, we apply the group Lasso regularization method during training process and learn a structural sparse model from scratch. Then the learned sparse structures will be fixed and cannot be changed. Finally, we retrain the model and update the nonzero parameters in the model. We applied our ESS method on classic HMM+LSTM model on Kaldi toolkit. The experimental results show that ESS can remove 72.5% weight groups in the weight matrices when slightly increasing the word error rate (WER) 1.1%.
Jingchi Zhang, Wei Wen 0003, Michael Deisher, Hsin-Pai Cheng, Hai Li 0001, Yiran Chen 0001
ICASSP3
2017 Implementation of efficient, low power deep neural networks on next-generation intel client platforms
abstract
In recent years many signal processing applications involving classification, detection, and inference have enjoyed substantial accuracy improvements due to advances in deep learning. At the same time, the “Internet of Things” has become an important class of devices. Although the paradigm of local sensing and remote inference has been very successful (e.g., Apple Siri, Google Now, Microsoft Cortana, Amazon Alexa, and others) there exist many valuable applications where sensing duration is very long, the cost of communication is high, and scaling to millions or billions of devices is not practical. In such cases, local inference “at the edge” is attractive provided it can be done without compromising accuracy and within the thermal envelope and expected battery life of the edge device.
Michael Deisher, Andrzej Polonski
ICASSP1
2017 Speech Recognition and Understanding on Hardware-Accelerated DSP
Georg Stemmer, Munir Georges, Joachim Hofer, Piotr Rozen, Josef G. Bauer, Jakub Nowicki, Tobias Bocklet, Hannah R. Colett, Ohad Falik, Michael Deisher, Sylvia J. Downing
INTERSPEECH10
2010 Novel CI-backoff scheme for real-time embedded speech recognition
abstract
A new method for reduction of computation and memory bandwidth for embedded large vocabulary continuous speech recognition is presented. During the Hidden Markov model state likelihood computation, scores for selected context-dependent (triphone) model states are computed for several frames in advance. Scores that are subsequently needed for Viterbi search but not found in the buffer are replaced by the scores for associated context independent (monophone) models. On the Wall Street Journal 20,000 word continuous speech recognition task, an overall reduction of 58% memory bandwidth and decrease of 23% execution time is achieved relative to an assembly optimized implementation of Sphinx 3. Recognition accuracy is reduced by <;1% while recognition latency is increased by 30 milliseconds.
Michael Deisher
ICASSP2
2010 Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU
abstract
Recent advances in computing have led to an explosion in the amount of data being generated. Processing the ever-growing data in a timely manner has made throughput computing an important aspect for emerging applications. Our analysis of a set of important throughput computing kernels shows that there is an ample amount of parallelism in these kernels which makes them suitable for today's multi-core CPUs and GPUs. In the past few years there have been many studies claiming GPUs deliver substantial speedups (between 10X and 1000X) over multi-core CPUs on these kernels. To understand where such large performance difference comes from, we perform a rigorous performance analysis and find that after applying optimizations appropriate for both CPUs and GPUs the performance gap between an Nvidia GTX280 processor and the Intel Core i7-960 processor narrows to only 2.5x on average. In this paper, we discuss optimization techniques for both CPU and GPU, analyze what architecture features contributed to performance differences between the two architectures, and recommend a set of architectural features which provide significant improvement in architectural efficiency for throughput kernels.
Victor W. Lee, Changkyu Kim, Jatin Chhugani, Michael Deisher, Daehyun Kim 0001, Anthony D. Nguyen, Nadathur Satish, Mikhail Smelyanskiy, Srinivas Chennupaty, Per Hammarlund, Ronak Singhal, Pradeep Dubey
ISCA4