Amplitude-integrated electroencephalography (aEEG), a time compression technique, compresses the time scale of the conventional electroencephalogram (EEG) which is advantageous for presenting long EEG recordings. Cerebral function monitors use a reduced number of electrodes from the standard 10-20 montage and displays both an EEG and aEEG trace from one or two channels. Sleep-wake cycling is defined as a state of continuous normal voltage and the presence of both wakefulness or active sleep and quiet sleep with a minimum of two or three consecutive sleep state changes on aEEG for a duration of twenty minutes during a three-four hour period. Sleep-wake cycling in infants is often used as an indicator of the patient's neurological development and response to brain injury. There has been complete absence of algorithm development for the automated detection of changes in normal neonatal sleep-wake cycling patterns displayed by cerebral function monitor. This study will incorporate a unique, robust algorithm for incorporation into a multidimensional data analysis environment, which is capable of capturing multiple individual streams of physiological data from bedside monitors and processing them. The framework supports the acquisition, collection, transmission, real-time processing, storage and retrospective analysis of wave form and physiological data streams combined with supporting clinical information including clinical observations and the results of laboratory investigations. The development of a robust, accurate and reliable algorithm that detects sleep-wake cycling in newborn infants greater than 29 weeks gestational age should provide valuable information for meaningful clinical decision support for physicians caring for critically ill neonates. This paper describes the development and results of the algorithm, its upper and lower boundary detection, low pass filtration, and threshold classification on an individual patient's data set.

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In this paper we present an innovative methodology to estimate and improve the quality of analog and mixed-signal circuit testing. We first detect and reduce the redundancy in the electrical test measurements (e-tests), then we identify the e-test acceptability regions by considering performance specifications as well as process parameter distributions. Finally, we provide an effective metric for the accurate assessment of the parametric test coverage of embedded analog IP. Experimental results confirm the validity of the proposed methodology and its broad applicability to analog, mixed-signal and RF applications for different process technologies.

This paper presents a new statistical methodology to simulate the effect of both inter-die and intra-die variation on the electrical performance of analog integrated circuits. The main feature of this methodology is that it accounts for device mismatch by using a number of variables that is asymptotically constant in the limit of perfectly matching devices, and is typically close to the number of independent process factors normally used to account for inter-die process variations only. A unified model of process variation allows the effects of each source of variation and their joint impact to be estimated, thus providing designers more accurate analysis and variance optimization capability. State-of-the-art application examples demonstrate the accuracy and efficiency of this approach.