This article investigates the attack detection for multisensor cyber-physical systems with both secure and insecure sensors as well as unknown-but-bounded noises based on a zonotopic approach. Based on the intersection of the predicted state set and the secure measurement state set, we construct the security state set to detect attacks on insecure sensors. Then the attacks can be detected by judging whether the intersection of the security state set and insecure measurement state set is empty. Then, we provide a sufficient condition to guarantee that the detection performance of our proposed method is better than that of the predicted state set-based method. Furthermore, we propose a watermarking-based detection method to detect attacks whose amplitude is within the zonotope of the measurement noise, and randomly select the watermarking within a center-constrained zonotope. The watermarking is utilized to ensure that the measurement output with watermarking is not equal to zero, which can enhance the detection performance of our proposed method. Finally, a numerical simulation is provided to demonstrate the effectiveness of theoretical results.

Most existing computer architecture simulators are cycle oriented, i.e., they are driven cycle by cycle. However, frequent switches among simulation contexts, excessive buffer accesses and tightly coupled manner often make such an architecture simulator slow, difficult to parallelize and hard to scale to large-scale many-core systems. In this paper, we propose Prophet, a parallel instruction-oriented simulation framework for many-cores. Prophet adopts a general instruction-oriented model to simulate processor cores, in which a simulator is built from the perspective of each simulated instruction impacting a small number of relevant processor components, as opposed to that of a large number of processor components executing many instructions in each cycle as in the cycle-oriented approach. Prophet determines the execution cycle of a simulated instruction based on the states of the relevant components impacted by the instruction, and update the components states after the execution of the instruction. Prophet also adopts a speculative model to decouple private resources from the shared resources (e.g., shared cache), which avoids unnecessary interactions between them and only pays a penalty upon a rare mis-speculation. We have designed and implemented a prototype of Prophet that supports both user-level and full-system simulation. Experimental results show Prophet can scale up to simulate thousands of simulated cores (4,096 cores in the current implementation) with good performance and small accuracy loss. It achieves average simulation speeds of about 98 and 235 MIPS (millions of simulated instructions per second) for full-system and user-level simulation, respectively, with only 3 percent IPC error rate and negligible deviation in cache simulation results. When run on a many-core platform (i.e., Intel Xeon Phi), it achieved an average simulation speed of about 413 MIPS.

Detecting concurrency bugs, such as data race, atomicity violation and order violation, is a cumbersome task for programmers. This situation is further being exacerbated due to the increasing number of cores in a single machine and the prevalence of threaded programming models. Unfortunately, many existing software-based approaches usually incur high runtime overhead or accuracy loss, while most hardware-based proposals usually focus on a specific type of bugs and thus are inflexible to detect a variety of concurrency bugs. In this paper, we propose Hydra, an approach that leverages massive parallelism and programmability of fused CPU-GPU architectures to simultaneously detect multiple concurrency bugs in threaded software, including data race, atomicity violation and order violation. Hydra extends contemporary fused CPU and GPU by introducing two modules: 1) a trace collecting module (TCM) that instruments and collects program behavior on CPU; 2) a trace preprocessing module (TPM) that processes and then transfers the traces to GPU for bug detection. Furthermore, Hydra exploits three optimizations to improve speed and accuracy, which includes: 1). using the bloom filter to filter out unnecessary traces; 2). avoiding eviction of shared traces; 3). comparing only last-write traces for shared data with the happens-before relation. Hydra incurs small hardware complexity and requires no changes to internal critical-path processor components such as cache and its coherence protocol, and is with about 1.1 percent hardware overhead under a 32-core configuration. Experimental results show that Hydra only introduces about 0.18 percent overhead on average for detecting one type of bugs and 0.46 percent overhead for simultaneously detecting multiple bugs, yet with the similar detectability of a heavyweight software bug detector (e.g., Helgrind).

Full-system simulation is critical in evaluating design alternatives for multicore processors. However, state-of-the-art multicore simulators either lack good extensibility due to their tightly-coupled design between functional model (FM) and timing model (TM), or cannot guarantee cycle-accuracy. This paper conducts a comprehensive study on factors affecting cycle-accuracy and uncovers several contributing factors less studied before. Based on these insights, we propose a loosely-coupled functional-driven full-system simulator for multicore, namely Transformer. To ensure extensibility and cycle-accuracy, Transformer leverages an architecture-independent interface between FM and TM and uses a lightweight scheme to detect and recover from execution divergence between FM and TM. Built upon Transformer and its foundational simulator components, a graduate student only needed to write about 180 lines of code to extend an X86 functional model (QEMU) in Transformer. Moreover, the loosely-coupled design also removes the complex interaction between FM and TM and opens the opportunity to parallelize FM and TM to improve performance. Experimental results show that Transformer achieves an average of 8.4 and 7.0 percent performance improvement over GEMS in 4-core and 8-core configuration while guaranteeing cycle-accuracy. A further parallelization between FM and TM leads to 35.3 and 29.7 percent performance improvement respectively.

Detecting concurrency bugs, such as data race, atomicity violation and order violation, is a cumbersome task for programmers. This situation is further being exacerbated due to the increasing number of cores in a single machine and the prevalence of threaded programming models. Unfortunately, many existing software-based approaches usually incur high runtime overhead or accuracy loss, while most hardware-based proposals usually focus on a specific type of bugs and thus are inflexible to detect a variety of concurrency bugs. In this paper, we propose Hydra, an approach that leverages massive parallelism and programmability of fused GPU architecture to simultaneously detect multiple types of concurrency bugs, including data race, atomicity violation and order violation. Hydra instruments and collects program behavior on CPU and transfers the traces to GPU for bug detection through on-chip interconnect. Furthermore, to achieve high speed, Hydra exploits bloom filter to filter out unnecessary detection traces. Hydra incurs small hardware complexity and requires no changes to internal critical-path processor components such as cache and its coherence protocol, and is with about 1.1% hardware overhead under a 32-core configuration. Experimental results show that Hydra only introduces about 0.35% overhead on average for detecting one type of bugs and 0.92% overhead for simultaneously detecting multiple bugs, yet with the similar detectability of a heavyweight software bug detector (e.g., Helgrind).

Nowadays, the release of SoC products has come to a burst. Time-to-market of these products has been shortened to an extreme, nearly 8 to 12 months. To reduce production period, hardware architects generally combine well-tuned IP cores in their designs. To guarantee the process of SoC software development, which will finally decide the release time of products, a fast prototyping simulation platform for SoC software development should be available as soon as possible after hardware design. However, state-of-the-art SoC simulators lack the support for fast integration of IP core and require time-consuming compiler chain modifications for new instructions. In this paper, we present Prism, an extensible and easy-to-use full-system SoC simulation platform for SoC software development. Two mechanisms are designed and implemented to support fast prototyping for new IP core simulation or new instruction extension without compiler tool chain modifications. First, a hardware and software hybrid mechanism is proposed for IP core fast prototyping. A seamless interface is used to eliminate the differences among IP cores. Second, a configurable library mechanism is designed for new instruction extension. Register dependence can be maintained for detailed timing simulation without compiler tool chain modification. In such a design, the major effort for extension is to specify the elaborate common customization interface. Experimental results show these mechanisms only involve about 0.36% runtime overhead. Based on RPSim, a graduate student only needs write about 40 lines of code and takes less than half an hour to extend a new IP core simulation in RPSim.

With the proliferation of mobile devices, an increasing number of urban users subscribe to location-based services. This trend has led to significant research interest in techniques that address two fundamental requirements: road network-based distance computation and the capability to process moving objects as points of interests. However, there exist few techniques that support both requirements simultaneously. To address these challenges, we propose a novel approach to process continuous range queries. We build on our previous work of an infrastructure that supports location-based snapshot queries on MOVing objects in road Networks (MOVNet). We introduce several significant features to enable continuous queries. The dual index structure that we proposed for MOVNet has been appropriately modified. We further appoint a number of connecting vertices in each cell and precompute the distances among them to expedite query processing. Most importantly, to alleviate the effects of frequent object updates, we introduce a Shortest-Distance-based Tree (SD-Tree). We illustrate that the network connectivity and distance information can be preserved and reused by the SD-Tree when the query point location is updated; hence, reducing the continuous query update cost. Our experimental results demonstrate that our method yields excellent performance with a very large number of moving objects.

Location-based services are increasingly popular recently. Many applications aim to support a large number of users in metro area (i.e., dense networks). To cope with this challenge, we present a framework that supports location-based services on MOVing objects in road Networks (MOVNet, for short) [26]. MOVNet's dual-index design utilizes an on-disk R-tree to store the network connectivities and an in-memory grid structure to maintain moving object position updates. In this paper, we extend the functionality of MOVNet to support snapshot range queries as well as snapshot k nearest neighbor queries. Given an arbitrary edge in the space, we analyze the minimum and maximum number of grid cells that are possibly affected. We show that the maximum bound can be used in snapshot range query processing to prune the search space. We demonstrate via theoretical analysis and experimental results that MOVNet yields excellent performance with various networks while scaling to a very large number of moving objects.

The PLUS system is designed to efficiently track moving object locations on a road network and execute continuous spatial queries in support of location-based services. PLUS implements a novel lazy position update mechanism that significantly reduces the communication overhead and server indexing load related to frequent location updates in moving object and moving query scenarios. The contribution of this demo is to present how the lazy position update scheme can achieve message-efficiency under various conditions which can be interactively set via user-selectable parameters in a graphical user interface.

Location-based services are increasingly popular and it is a key challenge to efficiently support query processing. We present a novel design to process large numbers of location-based snapshot queries on MOVing objects in road Networks (MOVNet, for short). MOVNet's dual-index design utilizes an on-disk R-tree to store the network connectivities and an in-memory grid structure to maintain moving object position updates. A method to speedily compute the overlapping grid cells in the network relates these two indices. Based on the above features we propose algorithms to support mobile network distance range queries. We demonstrate via experimental results that MOVNet yields excellent performance while scaling to a very large number of moving objects.

Continuous spatial queries posted within an environment of moving objects produce as their results a time-varying set of objects. In the most ambitious case both queries and data objects are dynamic, making it very challenging to find an efficient query evaluation strategy. The significant overhead related to frequent location updates from moving objects often results in poor performance. The most advanced existing techniques use the concept of simple geometric safe regions to delay or avoid location updates. We introduce a Partition-based Lazy Update (PLU) algorithm that elevates this idea further by adopting Location Information Tables (LIT) which (a) allow each moving object to estimate possible query movements and issue a location update only when it may affect any query results and (b) enable smart server probing that results in fewer messages. Among the significant advantages, our technique performs well even in very highly dynamic environments (with up to 100% mobility) where many other techniques deteriorate. PLU can be efficiently implemented and we demonstrate its query performance improvement of up to 28% over the current state-of-the-art.

In this demonstration we present MAPLE, a scalable peer-to-peer nearest neighbor (NN) query system for mobile environments. MAPLE is designed for the efficient sharing of query results cached in the local storage of mobile peers. The MAPLE system is innovative in its ability to either fully or partially compute location-dependent nearest neighbor objects on each host. The demonstration illustrates how cooperative data sharing and distributed processing among mobile peers results in a considerable reduction of the load on remote spatial databases.

Nearest neighbor (NN) searches represent an important class of queries in geographic information systems (GIS). Most nearest neighbor algorithms rely on static distance information to compute NN queries (e.g., Euclidean distance or spatial network distance). However, the final goal of a user when performing an NN search is often to travel to one of the search results. Based on this observation, finding the nearest neighbors in terms of travel time is more realistic than the actual distance. In the existing NN algorithms dynamic real-time events (e.g., traffic congestions, detours, etc.) are usually not considered and hence the pre-computed nearest neighbor objects may not accurately reflect the shortest travel time. In this demonstration we present ANNATTO, a novel adaptive nearest neighbor query model for travel time networks which integrates both spatial networks and real-time traffic event information. The ANNATTO system includes the implementation of a globalbased adaptive nearest neighbor algorithm and a localbased greedy nearest neighbor algorithm that both utilize real-time traffic information to provide adaptive nearest neighbor search results.